KR950021160A - Test pattern manufacturing method to see overlap margin of gate electrode - Google Patents
Test pattern manufacturing method to see overlap margin of gate electrode Download PDFInfo
- Publication number
- KR950021160A KR950021160A KR1019930030790A KR930030790A KR950021160A KR 950021160 A KR950021160 A KR 950021160A KR 1019930030790 A KR1019930030790 A KR 1019930030790A KR 930030790 A KR930030790 A KR 930030790A KR 950021160 A KR950021160 A KR 950021160A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- test pattern
- overlap margin
- oxide film
- metal line
- Prior art date
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 게이트전극(4)에 접속되는 금속라인과의 오버랩 마진을 보기 위한 테스트 패턴 제조방법에 있어서, 반도체기판(1)상에 필드산화막(6)을 형성하는 단계; 상기 필드산화막(6) 상에 소정 크기를 갖는 게이트전극을 형성하는 단계; 금속라인(5)을 상기 게이트전극(4)에 접속시키는 단계를 포함하여 이루어지는 것을 특징으로 하는 게이트전극의 오버랩 마진을 보기 위한 테스트 패턴 제조방법에 관한 것으로, 미스얼라인시 게이트산화막의 어택을 제거함으로써 금속라인과 기판 사이의 전도성을 명확하게 측정할 수 있도록 하여 고집적 반도체 소자의 설계와 불량분석을 전기적이고, 통계적으로 많은 양의 데이타를 활용할 수 있는 효과가 있다.The present invention provides a method of manufacturing a test pattern for seeing an overlap margin with a metal line connected to a gate electrode (4), comprising the steps of: forming a field oxide film (6) on a semiconductor substrate (1); Forming a gate electrode having a predetermined size on the field oxide film (6); A method of manufacturing a test pattern for seeing an overlap margin of a gate electrode, comprising the step of connecting a metal line (5) to the gate electrode (4), to remove the attack of the gate oxide film during misalignment Therefore, the conductivity between the metal line and the substrate can be clearly measured, and thus, the design and failure analysis of the highly integrated semiconductor device can be utilized electrically and statistically a large amount of data.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 게이트전극의 오버랩 마진을 보기 위한 테스트 패턴 형성도로서 정상적인 패턴을 가진 예시도2 is a test pattern formation diagram for viewing the overlap margin of the gate electrode according to the present invention, an exemplary view having a normal pattern
제3도는 본 발명에 따른 게이트전극의 오버랩 마진을 보기 위한 테스트 패턴 형성도로서 비정상적인 패턴을 가진 예시도.3 is a test pattern formation diagram for viewing the overlap margin of the gate electrode according to the present invention an exemplary view having an abnormal pattern.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930030790A KR950021160A (en) | 1993-12-29 | 1993-12-29 | Test pattern manufacturing method to see overlap margin of gate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930030790A KR950021160A (en) | 1993-12-29 | 1993-12-29 | Test pattern manufacturing method to see overlap margin of gate electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR950021160A true KR950021160A (en) | 1995-07-26 |
Family
ID=66853118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930030790A KR950021160A (en) | 1993-12-29 | 1993-12-29 | Test pattern manufacturing method to see overlap margin of gate electrode |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950021160A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100895817B1 (en) * | 2007-10-22 | 2009-05-08 | 주식회사 하이닉스반도체 | Test pattern of semiconductor device |
-
1993
- 1993-12-29 KR KR1019930030790A patent/KR950021160A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100895817B1 (en) * | 2007-10-22 | 2009-05-08 | 주식회사 하이닉스반도체 | Test pattern of semiconductor device |
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| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |