KR950015636A - Gate oxide film formation method of a semiconductor device - Google Patents

Gate oxide film formation method of a semiconductor device Download PDF

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Publication number
KR950015636A
KR950015636A KR1019930024970A KR930024970A KR950015636A KR 950015636 A KR950015636 A KR 950015636A KR 1019930024970 A KR1019930024970 A KR 1019930024970A KR 930024970 A KR930024970 A KR 930024970A KR 950015636 A KR950015636 A KR 950015636A
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KR
South Korea
Prior art keywords
oxide film
gate oxide
semiconductor device
forming
film formation
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Application number
KR1019930024970A
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Korean (ko)
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KR960016830B1 (en
Inventor
엄금용
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR93024970A priority Critical patent/KR960016830B1/en
Publication of KR950015636A publication Critical patent/KR950015636A/en
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Publication of KR960016830B1 publication Critical patent/KR960016830B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자의 게이트 산화막을 형성하는 방법에 관한 것으로, 게이트 산화막 성장시 저온 산화막 성장방법으로 성장시키되, 주산화공정에서 DCE(Dichloroethylene)의 양을 0.47∼0.85 SLPM(Standard Litter Per Minute)으로 증가시키거나, 어닐링(Annealing) 공정에서 온도를 850∼900℃로 상승시켜 게이트 산화막을 형성하므로써, 저온 산화막 성장방법으로 성장할 때 발생되는 고정전하(Fixed Charge)와 트랩전하(Interface Trap Charge) 등을 제거하여 실리콘 기판과 게이트 산화막간의 접촉(Interface)특성을 향상시킬 수 있는 반도체 소자의 게이트 산화막을 형성하는 방법에 관해 기술된다.The present invention relates to a method of forming a gate oxide film of a semiconductor device, wherein the gate oxide film is grown by a low temperature oxide film growth method, but the amount of DCE (Dichloroethylene) in the main oxidation process is 0.47 ~ 0.85 SLPM (Standard Litter Per Minute) By increasing the temperature or increasing the temperature to 850 ~ 900 ℃ in the annealing process to form a gate oxide film, fixed charges and trap charges generated when growing by low temperature oxide film growth method A method of forming a gate oxide film of a semiconductor device which can be removed to improve the interface characteristics between the silicon substrate and the gate oxide film is described.

Description

반도체 소자의 게이트 산화막 형성방법Gate oxide film formation method of a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (2)

게이트 산화막을 형성시킬 웨이퍼를 반응로에 장착한 후, 저온 산화공정과 어닐링공정으로 이루어지는 반도체 소자의 게이트 산화막 형성방법에 있어서, 온도를 700℃로 하고 개스 분위기를 O2: H2: DCE=8 : 8 : 0.47∼0.85 SLPM의 비율로 하여 산화공정을 실시한 후 어닐링공정을 통하여 게이트 산화막을 형성하는 것을 특징으로 하는 게이트 산화막 형성방법In the method for forming a gate oxide film of a semiconductor device comprising a low-temperature oxidation process and an annealing process, after mounting a wafer on which a gate oxide film is to be formed, the temperature is set to 700 ° C. and the gas atmosphere is set to O 2 : H 2 : DCE = 8. : 8: A gate oxide film forming method characterized in that a gate oxide film is formed through an annealing process after an oxidation process at a ratio of 0.47 to 0.85 SLPM. 게이트 산화막을 형성시킬 웨이퍼를 반응로에 장착한 후, 저온 산화공정과 어닐링공정으로 이루어지는 반도체 소자의 게이트 산화막 형성방법에 있어서, 저온 산화공정으로 산화막을 성장시킨 후 850∼900℃의 고온으로 어닐링 공정을 실시하여 게이트 산화막을 형성하는 것을 특징으로 하는 게이트 산화막 형성 방법.In the method of forming a gate oxide film of a semiconductor device comprising a low temperature oxidation process and an annealing process after mounting a wafer on which a gate oxide film is to be formed, the annealing process is performed at a high temperature of 850 to 900 占 폚 after the oxide film is grown by a low temperature oxidation process. Performing a gate oxide film to form a gate oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93024970A 1993-11-23 1993-11-23 A method for forming gate oxide of semiconductor device KR960016830B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93024970A KR960016830B1 (en) 1993-11-23 1993-11-23 A method for forming gate oxide of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93024970A KR960016830B1 (en) 1993-11-23 1993-11-23 A method for forming gate oxide of semiconductor device

Publications (2)

Publication Number Publication Date
KR950015636A true KR950015636A (en) 1995-06-17
KR960016830B1 KR960016830B1 (en) 1996-12-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR93024970A KR960016830B1 (en) 1993-11-23 1993-11-23 A method for forming gate oxide of semiconductor device

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Publication number Publication date
KR960016830B1 (en) 1996-12-21

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