KR950014678B1 - Super low type wirebonding method - Google Patents
Super low type wirebonding method Download PDFInfo
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- KR950014678B1 KR950014678B1 KR1019920022567A KR920022567A KR950014678B1 KR 950014678 B1 KR950014678 B1 KR 950014678B1 KR 1019920022567 A KR1019920022567 A KR 1019920022567A KR 920022567 A KR920022567 A KR 920022567A KR 950014678 B1 KR950014678 B1 KR 950014678B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000000630 rising effect Effects 0.000 claims abstract description 5
- 230000001174 ascending effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 241000587161 Gomphocarpus Species 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- -1 hydrogen salt Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78313—Wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/851—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector the connector being supplied to the parts to be connected in the bonding apparatus
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
제1a~g도는 종래의 본딩공정도.1a to g are conventional bonding process diagrams.
제2도는 종래의 볼본딩 상태도.2 is a conventional ball bonding state.
제3도는 본 발명의 캐필러리 요부정면도.3 is a capillary recessed front view of the present invention.
제4a~i도는 본 발명의 본딩공정도.4a to i is a bonding process diagram of the present invention.
제5도는 본 발명의 볼본딩 상태도이다.5 is a ball bonding state diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
3 : 와이어 11 : 선단부3: wire 11: tip
12 : 피딩홀12: feeding hole
본 발명은 웨지(Wedge)형 캐필러리를 사용하여 와이어를 볼본딩 및 스티치 본딩시켜 초저형(Low Loop) 와이어본딩을 가능케하는 초저형 와이어 본딩방법에 관한 것이다.The present invention relates to an ultra-low wire bonding method that enables low loop wire bonding by ball-bonding and stitch-bonding wires using a wedge capillary.
일반적으로 캐필러리는 반도체 조립공정중 본딩와이어를 칩의 패드와 리드에 연결시켜 주는 본딩도구로써, 칩과 리드를 본딩와이어를 이용하여 전기적으로 접속시켜 전기적 회로를 구성할 수 있도록 하는데 사용된다.In general, the capillary is a bonding tool that connects the bonding wires to the pads and the leads of the chip during the semiconductor assembly process. The capillary is used to electrically connect the chips and the leads using the bonding wires to form an electrical circuit.
이러한 캐필러리는 길이방향의 중앙에 미세한 피딩공이 형성되고 그 선단은 만곡면의 선단부를 이루어 인출된 본딩와이어를 가열상태로 눌러주어 칩과 리드를 와이어 본딩토록 하는 것이다.The capillary is formed with a fine feeding hole in the center of the longitudinal direction, the tip of the capillary is to form a tip of the curved surface to press the drawn bonding wire in a heated state to bond the chip and the lead to wire bonding.
이때 와이어 본딩법의 대표적인 예로는 볼본드법과 스티치법이 알려져 있는바, 볼본드법은 내일헤드 본딩(Nailhead Bonding)이라고도 부르며, 캐필러리의 인출공을 통하여 본딩와이어(금(Au)선)를 내보내고 이것을 캐필러리로 눌러붙이는 방법이다. 이에 반하여 스티치법은 필요한 부위에 방향에 구애받지 않고 압착시켜 본딩하는 방법을 말한다.At this time, the ball bonding method and the stitch method are known as a representative example of the wire bonding method, the ball bonding method is also called tomorrow head bonding (Nailhead Bonding), and the bonding wire (Au wire) through the drawing hole of the capillary It is a method of pressing this with a capillary. On the contrary, the stitch method refers to a method of bonding by bonding the necessary parts irrespective of the direction.
이를 도면을 참조하여 설명하면 제1a~g도는 종래의 와이어본딩 공정도로, 제1a도는 캐필러리(1)의 피딩공(2)에 와이어(3)가 인출된 상태에서 수소염등에 의해 와이어(3) 선단이 볼(4)상태를 이룬것을 도시한 것이며, 이때(5)는 다이, (6)은 다이(5)의 다이본딩패드이며, (7)은 와이어크램프이다. 이어 제1b도와 같이 캐필러리(1)가 하강하여 볼(4)이 다이본딩패드(6)에 본딩되도록 볼본딩 시킨다. 다음 제1c도와 같이 캐필러리(1)가 설정높이로 수직상승하여 캐필러리(1)가 머신상에 이미 메모리된 파라미터만큼 와이어 루프 높이(H1)를 형성하고(제1d도), 리드프레임의 내부리드(8) 위치로 이동한다(이때의 볼본딩 상태의 확대도는 제2도와 같다). 따라서 제1e도와 같이 내부리드(8)상에 와이어(3)를 본딩시킴과 동시에 절단한다(Stitch Bond). 이어 제1f도와 같이 캐필러리가 수직상승하여 일정길이의 와이어테일(3')을 유지한 다음 와이어크램프(7)가 크램핑하여 대기하고, 제1g도와 같이 스파크브레이드(9)등을 이용하여 새로운 볼(4')을 형성시켜 다음 본딩을 대비케한다. 상기 공정에서 와이어크램프(7)는 개폐를 반복하여 외이어피딩을 제어하는바, 제1f도에서는 와이어크램프(7)가 닫혀져서 캐필러리가 수직상승하는 동안 와이어(3) 자체는 고정되어 와이어테일(3')을 형성할 수 있도록 되지만, 그외의 공정에서는 와이어크램프(7)가 열려있는 상태로 와이어피딩이 자유롭게 된다. 그러나 이와같은 캐필러리를 이용한 본딩은 와이어루프 높이(H1)가 일정한 높이로 형성됨으로써, 이에따라 인캡슐레이션(Encapsulation ; 일명 Moldig)도 일정두께로 형성이 되어야 신뢰성을 보장할 수 있다. 결국 반도체 패키지의 두께가 반도체를 사용하는 모든 산업의 시스템 사이즈를 좌우하기 때문에 근본적인 와이어루프 높이는 시스템의 크기와 연결된다고 볼수있어, 와이어루프 높이가 높으면 시스템의 사이즈를 줄일수 없는 단점이 된다. 한편 세라믹 패키지등의 와이어본딩을 위하여는 A1 와이어등을 스티치본딩시키기 위하여 웨지형 캐필러리가 사용되고 있으나, 이는 단순한 스티치 본딩에 적합한 것으로 지향성이 있고 캐필러리는 상하 운동하고 하부의 패키지 부분이 움직여서 본딩토록 하는 것으로 볼본딩이 요구되는 플라스틱 패키지에는 사용될 수 없는 단점이 있었다.Referring to the drawings with reference to the drawings 1a to g is a conventional wire bonding process, Figure 1a is a wire (by hydrogen salt, etc. in a state in which the wire 3 is drawn out to the feeding hole 2 of the capillary 1 3) The tip is in the state of the ball (4), wherein (5) is a die, (6) is a die bonding pad of the die (5), (7) is a wire clamp. Subsequently, as shown in FIG. 1B, the capillary 1 is lowered to ball-bond the ball 4 to be bonded to the die bonding pad 6. Next, as shown in FIG. 1C, the capillary 1 rises vertically to the set height so that the capillary 1 forms the wire loop height H1 by the parameter already stored on the machine (FIG. 1D), and the lead frame It moves to the position of the inner lead 8 of (the enlarged view of the ball bonding state at this time is the same as FIG. 2). Therefore, the wire 3 is bonded and cut at the same time as shown in FIG. 1e (Stitch Bond). Subsequently, as shown in FIG. 1f, the capillary rises vertically to maintain the wire tail 3 'of a predetermined length, and then the wire clamp 7 is clamped to stand by. As shown in FIG. A ball 4 'is formed to prepare for the next bonding. In the above process, the wire clamp 7 controls the wire feeding by repeatedly opening and closing. In FIG. 1f, the wire 3 itself is fixed while the capillary rises vertically by closing the wire clamp 7. 3 'can be formed, but in other processes, the wire feeding is free with the wire clamp 7 being open. However, the bonding using the capillary is wire loop height (H1) is formed to a constant height, accordingly encapsulation (Encapsulation; also known as Moldig) can be formed to a certain thickness to ensure the reliability. After all, since the thickness of the semiconductor package depends on the size of the system in all industries that use the semiconductor, it can be said that the fundamental wire loop height is connected to the size of the system, and the high wire loop height cannot reduce the size of the system. Wedge type capillary is used for stitch bonding A1 wire for ceramic bonding, etc., but this is suitable for simple stitch bonding. It is directional and capillary moves up and down and the lower part of package moves. As a result, there is a drawback that cannot be used in plastic packages requiring ball bonding.
본 발명은 이를 해결코자 하는 것으로, 웨지(Wedge)형 캐필러리를 사용하여 볼본딩하고 볼본딩후 캐필러리의 상승을 경사지게 상승케하여 와이어루프 높이를 극소화시킬수 있도록 하는 본딩방법을 제공함을 특징으로 한다. 즉, 웨지형 캐필러리를 사용 볼본딩후 경사지게 설정된 파라미터만큼 상승하는 제1단계와 제1단계후 스티치 본딩할 부위로 이동하여 와이어 크램프가 닫힌 상태에서 스티치 본딩하는 제2단계와 스티치 본딩후 크램프를 해제하여 경사지게 상승한 후 수직상승하여 다음 볼본딩을 대비하는 제3단계를 한 싸이클로 하여 본딩하는 본딩방법이다.The present invention is to solve this problem, by using a wedge (capable) capillary ball bonding and after the ball bonding to increase the slope of the capillary to provide a bonding method for minimizing the height of the wire loop. do. In other words, the wedge-shaped capillary is moved to the first step and the step to be stitch-bonded after the first step to be inclined after the ball bonding, and the second step of stitch bonding in the state in which the wire clamp is closed and the clamp after the stitch bonding It is a bonding method in which the third step of preparing for the next ball bonding is performed as a single cycle after rising upwardly and inclinedly upward.
이하 본 발명의 실시예를 도면을 참조하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
제3도는 본 발명에 사용되는 웨지 캐필러리의 요부정면도로 캐필러리(10)는 그 선단부(11) 하부중앙에서 측면 임의개소로 관통되는 피딩공(12)이 경사지게 형성된다. 이러한 캐필러리를 사용하여 본딩하는 공정을 설명하면 제4a도와 같이 캐필러리(10)의 경사진 피딩홀(12)과, 피딩홀(12)의 경사진 수직선산에 와이어크램프(13)가 설치되고 와이어크램프(13)와 피딩홀(12)을 통해 와이어(3)가 피딩되며 선단부(11)로 와이어테일(14)이 일부 돌출케하여 초기상태를 이룬다. 이어 제4b도와 같이 스파크브레이드(9)등을 이용하여 캐필러리(10) 선단에 돌출된 와이어테일(14)을 볼(15)로 형성한다. 이때 볼(15) 하부에는 다이본딩패드(6)가 형성된 다이(5)가 위치되며 다이(5) 표면의 다이본딩 패드(6)이외 부분은 픽셀코팅(Pixel Coating)층(5')을 이룬다. 이어 제4c도와 같이 다이(5)의 다이본딩 패드(6) 위치로 캐필러리(10)가 수직하강하여 제4d도와 같이 다이본딩 패드(6)에 와이어(3)의 볼(15)이 접착되어 볼본딩을 이루고, 제4e도와 같이 캐필러리(10)의 피딩홀(12) 경사각도와 일치되도록 설정된 파라미터만큼 경사지게 상승이동하여 제1단계를 수행한다(이때의 볼본딩상태는 제5도와 같이 확대 예시할 수 있다). 이어 제4f도와 같이 설정된 파라미터에 따라 내부리드(8) 위치로 이동하고, 제4g도와 같이 와이어(3)를 내부리드(8)에 스티치본딩(Stitch Bonding) 시킨다. 이때 와이어(3)는 각 본드부위별로 메모리 되어있는 길이만큼 제어되는 것으로 제4f도에 도시한 바와같이 낮은 와이어루프 높이(H2)를 이룰수 있게된다(제2단계). 이어 제4h도와 같이 와이어(3)가 절단된 후 캐필러리(10)가 피딩홀(12)의 경사각도와 일치되게 상승하다가 제4a도에 도시한 와이어 크램프(13)가 닫히면서 수직상승하면, 스티치 본딩부위에서의 와이어(3)가 절단되어 제4i도와 같이 캐필러리(10)의 선단부(11)로 일정길이의 와이어테일(14)을 유지하여 다음 본딩에 필요한 볼을 형성토록 한다(제3단계). 물론 다음칩의 본딩을 위하여서는 캐필러리(10)가 다음번 위치로 이동함이 요구된다. 이와 같이 상기 제1~3단계를 차례로 반복하여 와이어본딩을 수행하면 제4f도와 같이 와이어루프 높이(H2)가 낮게되어 패키지의 두께를 줄일 수 있고, 와이어(3)의 와이어루프 높이(H2)가 낮으므로 그만큼 소요 와이어(3)양도 줄어들어 경제적이다. 본 발명에서의 캐필러리(10)를 사용하여 본 발명의 단계대로 수행하여 와이어본딩한 결과 종래의 와이어루프 높이(H1)가 4~6미리인치 임에 반하여 본 발명의 와이어루프 높이(H2)는 2~3미리인치로 낮출수 있음을 확인하였다.3 is a frontal view of the main portion of the wedge capillary used in the present invention, the capillary 10 is formed to be inclined the feeding hole 12 penetrated to any side of the lower end of the front end portion (11). Referring to the bonding process using the capillary, as shown in FIG. 4A, the wire clamp 13 is placed on the inclined feeding hole 12 of the capillary 10 and the inclined vertical line of the feeding hole 12. The wire 3 is fed through the wire clamp 13 and the feeding hole 12, and the wire tail 14 partially protrudes into the tip portion 11 to form an initial state. Subsequently, as shown in FIG. 4B, the wire tail 14 protruding from the tip of the capillary 10 using the spark blade 9 or the like is formed as the ball 15. In this case, a die 5 having a die bonding pad 6 is positioned below the ball 15, and portions other than the die bonding pad 6 on the surface of the die 5 form a pixel coating layer 5 ′. . Subsequently, the capillary 10 vertically descends to the position of the die bonding pad 6 of the die 5 as shown in FIG. 4C, and thus the ball 15 of the wire 3 is adhered to the die bonding pad 6 as shown in FIG. 4D. The ball bonding is performed, and the first step is performed by inclining ascendingly by a parameter set to match the inclination angle of the feeding hole 12 of the capillary 10 as shown in FIG. 4E (in this case, the ball bonding state is shown in FIG. 5). Can be expanded). Subsequently, it moves to the position of the inner lead 8 according to the parameter set as shown in FIG. 4f, and stitch-bonds the wire 3 to the inner lead 8 as shown in FIG. 4g. At this time, the wire 3 is controlled by the length stored in each bond portion, and as shown in FIG. 4f, it is possible to achieve a low wire loop height H2 (second step). Subsequently, after the wire 3 is cut as shown in FIG. 4h, the capillary 10 rises to coincide with the inclination angle of the feeding hole 12 and then rises vertically while the wire clamp 13 shown in FIG. 4a is closed. The wire 3 at the stitch bonding portion is cut to maintain the wire tail 14 having a predetermined length at the tip end portion 11 of the capillary 10 as shown in FIG. 4i so as to form a ball necessary for the next bonding. Step 3). Of course, the capillary 10 is required to move to the next position for bonding the next chip. As described above, if the wire bonding is performed by repeating the steps 1 to 3, the wire loop height H2 is lowered as shown in FIG. 4f to reduce the thickness of the package, and the wire loop height H2 of the wire 3 is increased. Since it is low, the quantity of required wires 3 is also reduced and it is economical. As a result of performing wire bonding using the capillary 10 in the present invention according to the steps of the present invention, the wire loop height H2 of the present invention is in contrast to the conventional wire loop height H1 of 4-6 mm. Confirmed that it can be reduced to 2-3mm.
이상과 같이 본 발명은 피딩홀을 경사지게 구성한 웨지 형태의 캐필러리를 사용하여 볼본딩후 경사지게 상승하여 와이어루프 높이를 줄일 수 있어 패키지를 박형화 시킬수 있고 이러한 캐필러리에 맞도록 경사지게 상승하여 설정 파라미터만큼 상승하는 등의 제조공정에 의해 볼본딩토록 함으로써 본딩와이어의 사용량을 줄일수 있다.As described above, the present invention uses a wedge-shaped capillary configured to be inclined to feed holes to be inclined after ball bonding to reduce the wire loop height, thereby making the package thin and inclined to fit such capillaries. It is possible to reduce the amount of use of the bonding wires by allowing ball bonding by a manufacturing process such as rising.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920022567A KR950014678B1 (en) | 1992-11-27 | 1992-11-27 | Super low type wirebonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920022567A KR950014678B1 (en) | 1992-11-27 | 1992-11-27 | Super low type wirebonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940012553A KR940012553A (en) | 1994-06-23 |
| KR950014678B1 true KR950014678B1 (en) | 1995-12-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920022567A KR950014678B1 (en) | 1992-11-27 | 1992-11-27 | Super low type wirebonding method |
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| KR (1) | KR950014678B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100309129B1 (en) * | 1995-12-01 | 2001-12-17 | 박종섭 | Wire bonding apparatus and bonding method using the same |
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1992
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| KR940012553A (en) | 1994-06-23 |
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