KR950014381B1 - Processing device of picture image - Google Patents

Abstract

a buffer processing unit for generating an acquirement request signal and a display request signal; a synchronization signal generating unit for providing a synchronization signal, and vertical and horizontal screen signals; a data transmission/reception controlling unit for inputting the acquirement request signal, the display request signal, and an output of the synchronization signal generating unit, and outputting a frame memory chip selecting signal for transmission/reception, a frame memory write signal for transmission, a frame memory write signal for reception, and an acquirement end signal, the data transmission/reception controlling unit being connected between the buffer processing unit and the synchronization signal generating unit; an address/data buffer for transmission operated by an input of an enable output signal of the data transmission/reception controlling unit; and an address/data buffer for reception operated by the input of the enable output signal of the data transmission/reception controlling unit.

Description

Image processing apparatus having data transmission / reception control circuit for still image telephone for general information communication network

1 is a schematic block diagram of an image processing apparatus according to the present invention;

FIG. 2 is a detailed circuit diagram of an embodiment of the image data transmission / reception control circuit of FIG.

* Explanation of symbols for main parts of the drawings

10,11: D flip-flop 20: to

24: NAND gate 30: AND gate

41:45: Inverter

50: to 55: OR gate

60 to 63 three-state buffer

111: chip select signal generation block 112: acquisition confirmation signal generation block

113: Transmission address / data enable signal generation block

114: Address / data enable signal generation block for reception

115: Frame memory signal generation block for transmission

116: reception frame memory signal generation block

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a circuit for controlling data transmission / reception data in an image processing unit of a still image telephone for an integrated telecommunication network. In particular, the image processing unit enables address / data buffers and transmits / receives image data to / from a buffer processing unit. An image processing apparatus having a data transmission and reception control circuit implemented in hardware.

Recently, due to the rapid development of the communication network, the video information communication technology is rapidly developing, and accordingly, the development of the still picture telephone in the existing telephone network has been made.

However, the conventional technology has a serious problem that it is impossible to transmit and receive a large amount of image information in a continuous and fast time due to the characteristics of the network.

Therefore, the present invention has been made to solve the above-mentioned problems, and while developing a video telephone capable of still image communication in a comprehensive information communication network, a function capable of simultaneously transmitting and receiving a large amount of image data in both directions at the same time. This critical requirement is a large amount of data in a short period of time by enabling the enable signals of the data and address buffer circuits required for the transmission and reception of image data, and the enable signals and read and write signals for the frame memory that stores the image data. It is an object of the present invention to provide an image processing apparatus having a data transmission / reception control circuit capable of transmitting and receiving data.

In order to achieve the above object, the present invention provides a butter processing means for generating an acquisition request (ACQ_REQ) signal and a display request (DISP_PEQ) signal in an image processing apparatus having a data transmission and reception control circuit: the synchronization signal and the vertical and horizontal screens. Synchronizing signal generating means for providing a signal: connected to said buffer processing means and synchronizing signal generating means, said synchronizing signal generating means being provided from said acquisition request (ACQ_REQ) and display request (DISPREQ) signals from said buffer processing means, and from said synchronizing signal generating means; A transmission and reception frame memory chip select signal, a transmission frame memory write signal, a reception frame memory read signal, an acquiring completion (ACQ_END) signal, for receiving and outputting a large amount of data simultaneously. And a data transmission / reception control circuit for generating a transmission / reception address / data enable signal. A transmit / receive address / data buffer configured to receive and operate an enable output signal of the data transmit / receive control circuit; and a receive address / data buffer configured to receive and operate an enable output signal of the data transmit / receive control circuit. .

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a schematic block diagram of an image processing apparatus according to the present invention, in which 100 is an image processing unit, 110 is an image data transmission and reception control circuit unit, 120 is a synchronization signal generation unit, 130 is a transmission / reception address / data buffer, and 140 is a number. The credit address / data buffer 200 denotes a buffer processing section, respectively.

As shown in the figure, the data transmission / reception control unit 110 in the image processing unit 100 according to the present invention receives an acquisition request (ACQ_REQ) signal from the buffer processing unit 200 and outputs an acquisition completion (ACQ_END) signal, and displays a display request. Receive the (DISP_REQ) signal. Subsequently, a reception frame memory read signal (/ R_FM_RD), a transmission / reception frame memory write signal (/ T_FM_WR), and a frame memory chip selection signal FM _CS are generated to control the transmission frame memory in the buffer processing unit 200. The vertical signal (VWNDW) signal, the horizontal screen (HWNDW) signal, the odd / even signal, the vertical synchronization signal VSYNC, and the divided clock signal 192FH are transmitted from the synchronization signal generator 110. The reception address / data buffer 130 and the reception address / data buffer 140 are enabled.

That is, the image processing unit 100 has an independent image address generation circuit on each of the transmission and reception sides, and the generated address signals are transmitted to the address buffers 130 and 140.

FIG. 2 is a detailed circuit diagram of an embodiment of the data transmission and reception controller 110 of FIG.

10 and 11 are D flip-flops, 20 to 24 are NAND gates, 30 are AND gates, 41 to 45 inverters, 50 to 55 OR gates, 60 to 3-state A buffer is 111, a chip select signal generation block, 112 is an acquisition confirmation signal generation block, 113 is a transmission address / data enable signal generation block, 114 is a reception address / data enable signal generation block, and 115 is a transmission frame. The memory read / chip select signal generation block 116 shows a receiving frame memory write / chip select signal generation block, respectively.

As shown in the figure, the data transmission / reception control unit 110 according to the present invention includes a chip select signal generation block 111, an acquisition signal generation block 112, and a transmission address / data enable signal generation block 113. ), A reception address / data enable signal generation block 114, a transmission frame memory read / chip selection signal generation block 115, and a reception frame memory write / chip selection signal generation block 116. Each function of these will be described as follows.

The frame memory chip select signal generation block 111 receives an acquisition request (ACQ_REQ) signal from the buffer processor 200 and generates a frame memory chip select (/ FM _CS: low signal in an active state) signal.

The acquisition completion signal generation block 112 is triggered by an odd / even signal generated from the synchronization signal generation unit 120 to generate a call from the frame memory chip select signal generation block 111. In response to the input, an acquisition completion (ACQ _ END) signal is generated, and the inversion signal of the acquisition completion (ACQ _ END) signal is applied to the frame memory chip select signal generation block 111.

The transmission address / data enable signal generation block 113 is perpendicular to the frame memory chip select (/ FM _ CS) signal, the frame memory chip select (FM _ CS) signal, and the synchronization signal generator 120. Each of the / horizontal screen (VWNDW / HWNDW) signals is applied to generate a transmission address / data enable signal (/ T_AD_EN, TDATA_EN).

The receiving address / data signal generating block 114 receives a display request (DISPREQ) signal from the buffer processing unit 200, and receives a vertical picture signal and a horizontal picture signal from the transmitting address / data enable signal generating block 113. A signal obtained by negatively multiplying the screen signal is input to generate a reception address / data enable signal (/ R_AD_EN, / RDAT A_EN).

The transmission frame memory signal generation block 115 includes a clock signal 192FH divided from the synchronization signal generator 120, the frame chip select signal FM_CS, and the transmission address / data enable. The frame frame chip selection signal (/ T_ FM _CS) for transmission and the frame frame write (/ T_ FM _WR) signal for receiving the vertical picture signal and the horizontal picture signal from the signal generation block 113 are negatively multiplied. Occurs each.

The reception frame memory signal generation block 116 includes a vertical screen (/ VWNDW) signal from the synchronization signal generator 120, a vertical screen signal from the transmission address / data enable signal generation block 113, and A signal obtained by multiplying a horizontal screen signal by a non-nonsense signal, the clock signal 192FH, and an inverted signal of the display request signal DISP_REQ applied to the reception address / data enable signal generation block 114 are respectively input. And a receiving frame memory chip select signal (/ R _ FM _ CS) and a receiving frame memory read (/ R _ FM _ RD) signal, respectively.

Now, the configuration of each of the signal generation blocks will be described in detail.

The frame memory chip select signal generation block 111 inputs an acquisition request (ACQREQ) signal from the buffer processing unit 200 to a column input terminal, and inputs an inverted signal of an acquisition completion (ACQ_END) signal to a type power stage. A signal obtained by inputting a negative-OR signal through the gate 20 to the preset terminal of the D flip-flop 10 at the next stage and inverting the output signal of the NAND gate 20 through the inverter 42 is the D flip. -Input to the clear terminal of the flop 10, the data input terminal to the D flip-flop 10 is grounded so that a 'low (0)' state is applied, and the positive output of the D flip-flop (10) Q) is connected to be input to the data input terminal of the other D flip-flop 11 at the rear stage. Then, the D flip-flop 11, which has received a value of '0' from the D flip-flop 10, is triggered by an ODD / EVEN clock from the synchronization signal generator 120. The frame memory chip select (/ FM _ CS) signal is output to the sub output terminal (/ Q).

The acquisition completion (ACQ _ END) signal generation block 112 uses the vertical synchronization signal VSYNC applied from the synchronization signal generator 120 as one input and outputs the odd / even signal. A NAND gate 22 that is negatively ANDed using the signal inverted through the inverter 43 as a type force, an output of the NAND gate 22, and a D flip-flop in the frame memory chip select signal generation block 111. A NAND gate 21 that negatively multiplies the positive output of 11 and an inverter 41 that inverts the output signal of the NAND gate 21, wherein the output signal of the NAND gate 21 is the frame memory chip. Connect to be applied to the NAND gate 20 in the selection signal generation block 111, the signal inverted through the inverter 41 is the acquisition completion signal (ACQ _ END) signal to inform that the image information for one frame is obtained As a transmission to the buffer processing unit 200.

The transmission address / data enable signal generation block 113 may include an AND gate 30 that logically multiplies the horizontal screen HWNDW signal and the vertical screen VWNDW signal applied from the synchronization signal generator l20; An inverter 44 for inverting the output of the AND gate, a NAND gate 23 having a frame memory chip select signal FM_CS as one input, and an output signal of the inverter 44 as a type force, and OR gate 50 having the inverted signal (/ FMCS) of the frame memory chip selection signal as one input and the output signal of the inverter 44 as a type force, for transmitting the result output of the OR gate 50. The data is output as a data enable signal T_DATA_EN, and the resultant output of the NAND gate 23 is output as a transmission address enable signal / T_AD_EN.

The reception address / data enable signal generation block 114 uses the signal inverted by the inverter 44 in the transmission address / data enable signal generation block 113 as one input and the buffer processor 200. NAND gate 24 which is applied to the display request signal DISP_REQ of the NAND by negative force, and inverts the display request signal DISP_REQ of the buffer processing unit 20, and the inverter. To an OR gate 55 for ORing the inverted display request signal DlSP_REQ applied via 45 and the signal inverted by inverter 44 in the transmission address / data enable signal generation block 113. And outputs a result output signal of the NAND gate 24 as a reception address enable signal (/ R _AD _EN), and a result output signal of the OR gate 55 is a data enable signal for reception (/ R _). DATA _ EN) Scene And outputs it as.

The transmission frame memory generation block 115 receives the frame memory chip selection signal / FM_CS as an input terminal and receives an inverted vertical screen signal / VWNDW as a control terminal for transmission frame memory chip selection signal. The clock signal divided by the clock of the synchronization signal generator 120 with the three-state buffer 60 generating (/ TFM_CS) and the frame memory chip select signal FM_CS as one input. OR gate 51 for ORing with 192FH as a type force, and an output of the OR gate 5l as one input, and inverter 44 in the address / data enable signal generation block 113 for transmission. Frame memory for transmission by receiving OR gate 52 for ORing with inverted signal as type force and output of OR gate 52 as input terminal and receiving inverted vertical screen signal / VWNDW to control terminal 3- generating a write signal (/ T_ FM _ WR) It is composed of state buffer 61.

The reception frame memory signal generation block 116 receives a display request signal inverted by the inverter 45 in the reception address / data enable signal generation block 114 to an input terminal and receives the inverted vertical screen signal. A 3-state buffer 62 receiving (/ VWNDW) as a control terminal and generating a receiving frame memory chip select (R _ FM _ CS) signal, and the receiving address / data enable signal generating block 114 An OR gate 53 for performing an OR operation with the display request signal inverted by the inverter 45 within as an input, and using the clock signal 192FH divided by the clock of the synchronization signal generator 120 as a type force; An OR gate 54 which uses the output of the OR gate 53 as one input and logically combines the signal inverted by the inverter 44 in the transmission address / data enable signal generation block 113 as a type force; OR above A tri-state buffer 66 that receives the output of the gate 54 as an input terminal and receives the inverted vertical screen signal / VWNDW as a control terminal and generates a receiving frame memory read signal / T_ FM _ RD. It consists of.

The present invention, through the configuration and operation as described above, by controlling the transmission and reception process of the image data of the stationary image telephone for the integrated information communication network, reading the transmission frame memory and the receiving frame memory for storing the image data to be transmitted and received, Generates a write signal and a chip select signal appropriately, generates a vertical synchronization signal, a vertical screen signal, and a horizontal screen signal for displaying image data on a screen, and receives an acquisition request signal to receive a chip select signal for a frame memory. Can also provide an acquisition complete signal as appropriate.

Therefore, the data transmission / reception control circuit of the still picture telephone according to the present invention enables the size of the frame memory to be expanded, and by appropriately adding circuit parts related to the camera and the monitor, the transmission of color images and moving images can be directly applied to a desired device. In particular, since it is composed of only general gate and flip-flop circuits, it is possible not only to transmit and receive a large amount of image information at the same time when transmitting image data, but also to effectively use in a data communication system that transmits and receives a large amount of data at the same time. .

Claims (8)

An image processing apparatus having a data transmission / reception control circuit, comprising: buffer processing means (200) for generating an acquisition request (ACQ _ REQ) signal and a display request (DISP_ REQ) signal: providing the synchronization signal and the vertical and horizontal screen signals Synchronization signal generating means 120: connected to the buffer processing means 200 and the synchronization signal generating means 120, the acquisition request (ACQ _ REQ) signal and display request (DISP_) from the buffer processing means 200 A REQ) signal, an output from the synchronization signal generating means 120, and a transmission and reception frame memory chip selection signal for simultaneously transmitting and receiving a large amount of data, a transmission frame memory write signal, and a number Data transmission / reception control circuit 110 generating a credit frame memory read signal, an acquisition completion (ACQ_END) signal, and a transmission / reception address / data enable signal. A transmission address / data buffer 130 which operates by receiving the enable output signal of the furnace 110; And a reception address / data buffer 140 for receiving and receiving an enable output signal of the data transmission / reception control circuit 110. Image processing apparatus. The method of claim 1, wherein the data transmission and reception control circuit 110 receives the acquisition request (ACQ _ REQ) signal from the buffer processing means 200, the frame memory chip select (/ FM _ CS: low in the active state) The frame memory chip selection signal generation block 111 for generating a signal); Triggered by an odd / even clock generated from the synchronization signal generating unit 120 and receiving an output from the frame memory chip select signal generation block 111 and acquiring an acq END signal. The frame memory chip select signal generation block 111 includes: an acquisition completion (ACQ_END) signal generation block 112 for applying an inverted signal of an acquisition completion (ACQ_END) signal; The frame memory chip select (/ FM _ CS) signal, the frame memory chip select (FM _ CS) signal, and the vertical / horizontal screen (VWNDW / HWNDW) signals are respectively received from the synchronization signal generator 120, The transmission / reception address / data enable signal generation block 113 for generating a transmission address / data enable signal (/ T_AD_EN, T_DATA_EN): A display request (DISP_REQ) from the buffer processing means 200. ) And a reception address / data enable signal (R _ AD _ EN, R _) received from the transmission / reception address / data enable signal generation block 113 by receiving a signal obtained by negatively multiplying the vertical screen signal and the horizontal screen signal. Reception address / data signal generation block 114 for generating DAT A_EN); A clock signal 192FH divided by the synchronization signal generating means 120, the frame chip select signal FM_CS signal, a vertical picture signal from the transmission address / data enable signal generating block 113, and A transmission frame memory signal that receives a signal obtained by negatively multiplying the horizontal picture signal and generates a transmission frame memory chip selection signal (/ T _ FM _ CS) and a transmission frame memory write (/ T_ FM _ WR) signal, respectively. Generation block 115; And a signal obtained by negatively multiplying a vertical screen (/ VWNDW) signal from the synchronization signal generating means 120, a vertical screen signal and a horizontal screen signal from the transmission address / data enable signal generation block 113, and A clock signal 192FH and an inverted signal of the display request signal DISP_REQ applied to the reception address / data enable signal generation block 114 are respectively inputted to receive a frame memory chip select signal (/ R_FM). _CS) and a receiving frame memory signal generating block 116 for generating a receiving frame memory read (/ R _ FM _ RD) signal, respectively. An image processing apparatus having a circuit. The method of claim 2, wherein the frame memory chip select signal generation block 111 takes an acquisition request (ACQ _ REQ) signal from the buffer processing unit 200 as one input and acquires acknowledgment (ACQ _) as a type force stage. END) signal, the first NAND gate 20 for inputting the inverted signal, the first inverter 42 for inverting the output signal of the first NAND gate 20, and the output of the first NAND gate 20. Is input as a preset terminal and the signal inverted by the first inverter 42 is input to the clear terminal, and the data input terminal is grounded 1D flip-flop 10, and the 1D flip-flop 10 The positive output Q is input to the data input terminal and the odd / even clock from the synchronization signal generating means 120 is input to the clock terminal, and the frame memory chip is selected to the sub output terminal (/ Q). 2D flip-flop (11) for outputting / FM _CS) signal An image processing apparatus having a data transmission and reception control circuit for a correction for a still image telephone network. The acquisition completion (ACQ_END) signal generating block 112 includes: a second inverter 43 for inverting the good / excellent signal obtained from the synchronization signal generating means 120, and the synchronization signal; A second NAND gate 22 which is negatively ANDed using the vertical synchronizing signal VSYNC from the generating means 120 as one input and the good / excellent signal inverted by the second inverter 43 as a type force; The output of the second NAND gate 22 is one input, and a type force stage receives an output from the frame memory chip select signal generation block 111 and performs an AND, and outputs the frame memory chip select signal generation block 111. A third inverter 41 for inverting an output of the third NAND gate 21 and an output of the third NAND gate 21 and transmitting an acquisition completion (ACQ_END) signal to the buffer processing means 200. Comprehensive information container characterized in that An image processing apparatus having a data transmission and reception control circuit for a reliable still image telephone. The transmission address / data enable signal generation block 113 is obtained by the synchronization signal generation means 120 with the frame memory chip select signal / FM_CS as one end of an input. An AND gate 30 that logically multiplies the horizontal screen signal HWNDW and the vertical screen VWNDW signal, a fourth inverter 44 that inverts the output of the AND gate 30, and a fourth inverter 44. The fourth NAND gate 23 generating a transmission address enable signal / T_AD_EN by performing an AND operation on the inverted signal as one input and the frame memory chip select signal FM_CS as a type force. ) And the output of the fourth inverter 44 as one input, and the frame memory chip select signal (/ FM _ CS) is used as a type force, and then the data enable signal T DATA _ EN is transmitted. Characterized in that it comprises a first OR gate (50) Sum information image processing apparatus having a data transmission and reception control circuit for a telephone network for the still picture. The reception address / data enable signal generation block 114 according to claim 5, wherein the reception address / data enable signal generation block 114 receives a signal from the fourth inverter 44 of the transmission address / data enable signal generation block 113 as one input. The type force stage is applied by the display request signal DISP_REQ of the buffer processing means 200, and is negatively multiplied. Then, the fifth NAND gate 24 which generates a receiving address enable signal R_AD_EN is generated. And a fifth inverter 45 for inverting the display request signal from the buffer processing means 200 and a signal from the fourth inverter 44 of the transmission address / data enable signal generation block 113. It is characterized in that the type force stage is provided with a second OR gate (55) for receiving the output signal of the fifth inverter (45) and logically combine to generate a receive data enable (/ R _ DATA _ EN) signal General information and communication network If an image processing apparatus having a data transmission and reception control circuit for a video phone. The transmission frame memory generation block 115 is configured to receive the frame memory chip select signal / FM_CS and generate a transmission frame memory chip select signal / T_FM_CS. A 13-state buffer 60 and the frame memory chip select signal FM_CS are input to one input, and a type-power stage receives and applies a clock signal 192FH divided by a clock of the synchronization signal generating means 120. A signal from the fourth inverter 44 of the transmission address / data enable signal generation block 113 with the third OR gate 51 for generating a signal and the output of the third OR gate 51 as one input. Second OR state buffer for generating the frame memory write signal (/ T _ FM _ WR) for transmission by inputting the fourth OR gate 52 which is ORed with the type force and the output of the fourth OR gate 52 A still image telephone for an integrated telecommunication network, comprising: 61 An image processing apparatus having a data transmission and reception control circuit for the device. The reception frame memory of claim 7, wherein the reception frame memory signal generation block 116 receives a signal from the fifth inverter 45 of the reception address / data enable signal generation block 114. A third tri-state buffer 62 for outputting a chip select signal / R _ FM _ CS and a signal from the fifth inverter 45 of the reception address / data enable signal generation block 114; The fifth OR gate 53 which is the one input and is logically summed by using the clock signal 192FH from the synchronization signal generation block 120 as the type force, and the output of the fifth OR gate 53 as one input, is used for the transmission. A sixth OR gate 54 for performing a logical OR using the signal from the fourth inverter 44 of the credit address / data enable signal generation block 113 as a type force and the output of the sixth OR gate 54 are inputted. Fourth tri-state generating a Credit Frame Memory Read (R _ FM_ RD) signal An image processing apparatus having a data transmitting / receiving control circuit for a still image telephone for an integrated information communication network, comprising a buffer (63).