KR950013874B1 - Track/holder circuit - Google Patents

Abstract

a first integrator for converting current which is input by synchronized with a rising edge of a clock into a voltage corresponding thereto; a second integrator connected in parallel to the first integrator, for converting the current which is input by synchronized with a falling edge of the clock into a voltage corresponding to the feedback of the output thereof; a hold switch connected between the first and second integrators, for alternately connecting the input terminal to the first and second integrators and applying the current; a selection switch for controlling the connection of the first and second integrators, input terminal and output terminal to transmit the output signal of the second integrator to the output terminal if the output signal of the first integrator is fedback to the input terminal and to transmit the output signal of the first integrator to the output terminal if the output signal of the second integrator is fedback to the input terminal; an output amplifier for amplifying and converting the signal transmitted to the output terminal; and a feedback amplifier for amplifying and converting the signal transmitted to the input terminal.

Description

Track / holder circuit

1 is a block diagram of a track / holder circuit according to the related art.

2 is a block diagram of a track / holder circuit according to the present invention;

3 is a timing diagram of FIG.

4 is a concrete circuit diagram of FIG.

* Explanation of symbols for main parts of the drawings

11: hold switch 13: first integrator

13 ': 2nd integrator 14: selection switch

15: feedback amplifier 17: output amplifier

The present invention relates to a track and holder circuit, and more particularly, to a track / holder circuit for improving the speed of an analog / digital (A / D) converter of a pipeline structure. will be.

The conventional track / holder circuit has an integrator 3 consisting of an amplifier A ₁ and a holder capacitor C ₁ , and G _mfb , a feedback trans conductance amplifier 5, as shown in FIG. 1. And G _mo , an output transconductance amplifier 17 for amplifying and outputting the voltage V _hold held by the holder capacitor C ₁ , and a hold switch 1 connected between an input terminal and the integrator 3. do.

Referring to the operation of the conventional track / holder circuit as described above, first, when the hold switch 1 is turned on, the input current I _In as a tracking mode passes through the integrator 3. The feedback transformer is converted into a voltage V _hold corresponding to the input current I _In .

Through a transconductance amplifier (5) G _mfb is converted into a feedback current I _fb, the feedback current I _fb is the input current (I _In) a difference from set to the error current (lerror) holder capacitors (C ₁ of the integrator (3) ) Is changed to the voltage (V _hold ) by charging or discharging, and eventually follows the magnitude of the input current (I _In ).

On the other hand, if the hold switch 1 is off (off), the feedback loop (feedback loop) is cut off in the hold mode, there is no current path (charge) to charge or discharge the holder capacitor (C ₁ ) the V _hold and the output current I _out of the output transconductance amplifier (7) G _mo and the output current I _fb of the _subtraction transconductance amplifier (5) maintain the value of that state. When applied to an A / D converter that is getting faster due to only one sampling during a colck) period, there is a problem that the sampling characteristics are deteriorated.

Accordingly, an object of the present invention is to connect the two integrators in parallel to solve the above problems, one to synchronize the rising edge of the clock, the other at the falling edge at the same time sampling at least two times per cycle It is to provide a track / holder circuit capable of realizing high speed by performing.

The track / holder circuit of the present invention for achieving the above object comprises a first integrator for converting the current I _in into a voltage corresponding to the input current in synchronization with the rising edge of the clock; A second integrator connected in parallel and converting a falling edge of the clock into a voltage corresponding to the input current and the feedback of its output, and connected between an input terminal and the first and second integrators, alternating with the input terminal; A hold switch for connecting the first and second integrators so that the current I _In is applied, and the output signal of the first integrator is fed back to the input terminal, so that the output signal of the second integrator is transmitted to the output terminal, Conversely, when the output signal of the second integrator is fed back to the input terminal, the output signal of the first integrator is transmitted to the output terminal of the first and second integrators, the input terminal and the output terminal. And a selection switch for controlling the connection, an output amplifier for amplifying and converting a signal transmitted to the output terminal, and a feedback amplifier for amplifying and converting a signal transmitted to the input terminal.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

The track / holder circuit of the present invention connects two integrators in parallel to enable two samplings during one clock period, so that they have twice the sampling rate as compared to a circuit using one integrator. Connect the selector switch to run on different clock edges.

That is, as shown in FIG. ₂ , the first integrator 13 and the second amplifier A ₃ made up of the capacitor C ₂ connected between the inverting input terminal and the output terminal of the first amplifier A ₂ . And a capacitor (C ₃ ) is connected to the second integrator (13 ') and the fixed terminal is connected to the input terminal, the same as the first integrator (13), the variable terminal ① of one side is connected to the first integrator (13) , The other variable terminal ② amplifies and converts the output voltage of the hold switch 11 connected to the second integrator 13 'and the first integrator 13 or the second integrator 13' to convert the current I _out . A feedback amplifier 15 for amplifying and converting an output amplifier 17 G _mo for outputting and an output signal of the first integrator 13 or the second integrator 13 'to feed back the current I _fb to the input terminal; G _mfb and an output terminal of the first integrator 13 and a first terminal ① are connected, and an input terminal and a second terminal of the output amplifier 17 G _mo . ④ is connected, and the input terminal of the second integrator 15 and the fourth terminal ⑥ is connected to each selector 14 is configured as a selector switch for operating at different clock edges.

The operation of the track / holder circuit constructed as described above with reference to the operation timing diagram of FIG. 3 is as follows.

First, the fixed terminal of the hold switch 11 is connected to the movable terminal ① of one side, the first terminal ③ and the fourth terminal ⑥ of the selection switch 14 is connected, the second terminal ④ and the third terminal

When ⑤ is connected, the first integrator 13 operates in a tracking mode and the second integrator 13 'operates in a hold mode.

That is, the input current I _in of the waveform as (A) is converted into the voltage V _{h1 of the} waveform as (C) corresponding to the input current I _in after passing through the first integrator 13. The feedback amplifier 15 is fed back to the input terminal with a feedback current I _fb to be equal to the input current I _in , where the capacitor C ₁ of the second integrator 13 ′ is filled. The discharge path is disconnected to maintain the current voltage (V _h2 ) and the output current value (I _out = G _mo · V _h2 ) does not change.

Subsequently, when the fixed terminal of the hold switch 11 is connected to the movable terminal ② of the other side, and the terminals of the selection switch 14 are connected to ③-④ and ⑤-⑥, the first integrator 13 is held. In this mode, since the second integrator 13 'operates in the tracking mode, the hold voltage V _hold is instantaneously at the voltage V _h2 across the capacitor C ₃ of the second integrator 13'. The voltage V _h1 across the capacitor C ₁ of the first integrator 13 is changed to remain in that state, and the output current value I _out = G _mo · V _h1 does not change.

In addition, the input current I _in is converted into a voltage corresponding to the input voltage through the second integrator 13 'and then fed back to the input terminal via the feedback amplifier 15.

That is, in the track / holder of the present invention, when the first integrator 13 tracks a signal while the fixed terminals of the hold switch 11 are alternately connected to the movable terminals ① and ② as described above, When the integrator 13 'holds the signal and then the first integrator 13 holds, the second integrator 13' repeats the process of tracking the signal to perform two samplings in one clock period. do.

FIG. 4 is a detailed circuit diagram of the track / holder circuit shown in the block diagram of FIG. 2 composed of BiCOMOS devices. Referring to FIG.

The hold switch 11 is composed of first and second transmission gates X ₁ and X ₂ , and the first integrator 13 has a drain connected to a power supply voltage V _DD . Two PMOS transistors M ₅ and M ₆ connected to each other by a gate, an N-mode transistor M ₃ connected to a drain of the PMOS transistor M ₅ , and a drain of the PMOS transistor M ₆ . An NMOS transistor (M ₄ ) connected with the base, and a base connected between the PMOS transistor (M ₅ ) and the NMOS transistor (M ₃ ), and a collector is a bipolar transistor (Q ₃ ) connected with the power supply voltage (V _DD ). And a capacitor C ₂ connected between the first transmission gate X ₁ of the hold switch 11 and the bipolar transistor Q ₃ , wherein the second integrator 13 ′ is the first integrator 13. ) and in the same manner connected PMOS transistors (M _9, M _10), NMOS It is transistors (M _7, M _8), and a bipolar transistor (Q ₄₎ and composed of a capacitor C _3.

In addition, the feedback amplifier 15 is composed of a resistor R ₁ connected between emitters of two bipolar transistors Q ₁ and Q ₂ , and G _mf , and the selection switch 17 is shown in FIGS. It is composed of four transmission gates X ₃ , X ₄ , X ₅ , X ₆ corresponding to the second, third and fourth terminals ③, ④, ⑤, ⑥, and the input current I _in is the hold switch ( When input to the first integrator 13 through the transmission gate (X ₁ ) of 11) this current charges the capacitor (C ₁ ), this voltage is the transmission gate (X ₃ ) of the selector switch 17 Is fed back through the feedback amplifier 15 to the input terminal, and the voltage held by the capacitor C ₃ of the second integrator 13 ′ is output through the transmission gate X ₆ of the selector switch 17. , and when the next input current I _in via a transmission gate (X ₂₎ of the hold switch 11 is input to the second integrator 13 ' The current is fed back to the input terminal via the feedback amplifier 15 through a transmission gate (X ₄₎ of the voltage is the selection switch 17 is again filled in, and fill, the capacitors (C _3), capacitors C _3, the The voltage held by the capacitor C ₂ of the first integrator 13 is output through the transmission gate X ₅ of the selection switch 17 to enable two samplings in one clock period.

Therefore, according to the present invention, by connecting two integrators in parallel as described above, the tracking and holding processes are alternately repeated in each integrator, thereby reducing the acquisition time since the loop is not broken. Since two samplings can be performed in a clock cycle, the A / D conversion can be performed twice as fast as the conventional A / D converter.

Claims (5)

The first integrator converts the current I _in when the current I _in is synchronized with the rising edge of the clock, and is connected in parallel with the first integrator and is synchronized with the falling edge of the clock. And a second integrator for changing to a voltage corresponding to the feedback of its output, connected between an input terminal and the first and second integrators, and connecting the first and second integrators alternately with the input terminal to supply current (I _in). Hold switch to be applied) and the output signal of the first integrator is fed back to the input terminal, the output signal of the second integrator is transmitted to the output terminal, and if the output signal of the second integrator is fed back to the input terminal, A selector switch controlling the connection of the first and second integrators, the input terminal and the output terminal to transmit the output signal of the first integrator to the output terminal; A signal amplifier, converts the signal to be transferred to the output amplifier and the input stage amplifier, converts the feedback amplifier to track / hold circuits which comprises having a to that. 2. The hold switch according to claim 1, wherein the hold switch has a first transmission gate (X ₁ ) connecting the input terminal and the first integrator when on, and a second transmission gate (X ₂ ) connecting the input terminal and the second integrator when on. A track / holder circuit, characterized in that consisting of. The method of claim 1 wherein the first integrator are each drain thereof is connected to the power supply voltage (V _DD), a source is connected to each other and the PMOS transistor M _5, M ₆ surrogate is connected each of the PMOS transistors M _5, M ₆ and the NMOS transistors M ₃ and M ₄ connected to the drain, and the base are connected between the PMOS transistor M ₅ and the NMOS transistor M ₃ , and the collector is connected to the bipolar transistor Q ₃ connected to the power supply terminal V _DD . And a capacitor C ₃ coupled between the first transmission gate X ₁ and the bipolar transistor Q ₃ . The third and sixth transmission gates of claim 1, wherein the selection switch is connected to each other when the first transmission gate X ₁ of the hold switch is turned on so that an output of the first integrator is applied to the feedback amplifier. X ₃ and X ₆ and the fourth and fifth transmission gates X ₄ and X _{5 which} are connected to each other when the second transmission gate X ₂ is turned on so that the output of the second integrator is applied to the feedback amplifier. A track / holder circuit comprising: a. The track / holder circuit according to claim 1, wherein the first and second integrators have the same integral constant.