KR950007300A - Track / holder circuit - Google Patents

Track / holder circuit Download PDF

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Publication number
KR950007300A
KR950007300A KR1019930016831A KR930016831A KR950007300A KR 950007300 A KR950007300 A KR 950007300A KR 1019930016831 A KR1019930016831 A KR 1019930016831A KR 930016831 A KR930016831 A KR 930016831A KR 950007300 A KR950007300 A KR 950007300A
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KR
South Korea
Prior art keywords
integrator
input terminal
output
transmission gate
terminal
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Application number
KR1019930016831A
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Korean (ko)
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KR950013874B1 (en
Inventor
박승균
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문정환
금성일렉트론 주식회사
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Priority to KR1019930016831A priority Critical patent/KR950013874B1/en
Publication of KR950007300A publication Critical patent/KR950007300A/en
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Publication of KR950013874B1 publication Critical patent/KR950013874B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

이 발명은 고속 A/D 변환기의 트랙/홀더 회로에 관한 것으로, 2개의 적분기를 병렬로 연결하여 각각의 적분기에서 궤환루프가 끊어지지 않도록 트랙킹과 홀딩과정을 교대로 반복함으로써, 1클럭주기에 2번의 샘플링을 수행하여 A/D변환속도를 향상시킬 수 있다.The present invention relates to a track / holder circuit of a high-speed A / D converter. By integrating two integrators in parallel, the tracking and holding processes are alternately repeated so that the feedback loop is not broken at each integrator. The A / D conversion speed can be improved by performing one sampling.

Description

트랙/홀더 회로Track / holder circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 트랙/홀더 회로의 구성 블록도2 is a block diagram of a track / holder circuit according to the present invention.

제3도는 제2도의 타이밍도3 is a timing diagram of FIG.

Claims (5)

전류(Iin)가 입력되면 이를 입력된 전류에 상응하는 전압으로 변환시키는 제1적분기(13)와, 상기 제1적분기(13)와, 병렬로 연결된 제2적분기(13')와, 입력단과 상기 제1 및 제2적분기(13,13') 사이에 연결되어 상기 입력단과 교대로 제1 및 제2적분기(13,13')를 접속하여 전류(Iin)가 인가되도록 하는 홀드스위치(11)와, 상기 제1적분기(13)의 출력신호를 입력단으로 궤환시키면, 상기 제2적분기(13')의 출력신호는 출력단으로 전송되도록 하고, 역으로 제2적분기(13')의 출력신호를 입력단으로 궤환시키면, 상기 제1적분기(13)의 출력신호를 출력단으로 전송되도록 제1 및 제2적분기(13,13'), 입력단 및 출력단의 접속을 제어하는 선택스위치(14)와, 상기 출력단으로 전송되는 신호를 증촉, 변환하는 출력증폭기(17) 및 상기 입력단으로 전송되는 신호를 증폭, 변환시키는 궤환증폭기(15)를 구비하여 이루어지는 것을 특징으로 하는 트랙/홀더 회로.The first integrator 13 converts the current Iin into a voltage corresponding to the input current, the first integrator 13, the second integrator 13 ′ connected in parallel, the input terminal and the A hold switch 11 connected between the first and second integrators 13 and 13 'to connect the first and second integrators 13 and 13' alternately with the input terminal so that a current Iin is applied thereto; When the output signal of the first integrator 13 is fed back to the input terminal, the output signal of the second integrator 13 'is transmitted to the output terminal, and conversely, the output signal of the second integrator 13' is input to the input terminal. When fed back, the selector switch 14 controls the connection of the first and second integrators 13 and 13 ', the input terminal and the output terminal to transmit the output signal of the first integrator 13 to the output terminal, and the output signal to the output terminal. An output amplifier 17 for boosting and converting a signal to be converted and a feedback amplifier for amplifying and converting a signal transmitted to the input terminal Track / hold circuits, characterized in that obtained by including a group (15). 제1항에 있어서, 상기 홀드스위치(11)는 온되면 입력단과 제1적분기(13)를 접속하는 제1트랜스미션 게이트(X1)와, 온되면 입력단과 제2적분기(13')를 접속하는 제2트랜스미션 게이트(X2)를 구비하여 이루어지는 것을 특징으로 하는 트랙/홀더 회로.2. The hold switch 11 according to claim 1, wherein the hold switch 11 connects the first transmission gate X 1 which connects the input terminal and the first integrator 13 when it is turned on, and the input terminal and the second integrator 13 'which is connected when it is turned on. A track / holder circuit comprising a second transmission gate (X 2 ). 제1항에 있어서, 제1적분기(13)는 각각 드레인이 전원전압(VDD)에 연결되고, 서로 게이트가 연결된 피모스 트랜지스터 M5,M6와, 서로 소스가 연결되고 각각 상기 피모스 트랜지스터 M5,M6와드레인이 연결된 엔모스 트랜지스터 M3,M4와, 베이스가 상기 피모스 트랜지스터 M5와 엔모스 트랜지스터 M3사이에 연결되며, 콜렉터는 전원단자(VDD)와 연결된 바이폴라 트랜지스터 Q3와, 상기 제1트랜스미션 게이트(X1)와 바이폴라 트랜지스터 Q3사이에 연결된 캐패시터 C2를 구비하여 이루어지는 것을 특징으로 하는 트랙/홀더 회로.The PMOS transistors of claim 1, wherein the drains of the first integrators 13 are connected to a power supply voltage V DD, respectively, and PMOS transistors M 5 and M 6 , each of which is gated to each other, are respectively connected to a source thereof, M 5 , M 6 and DMOS transistors M 3 and M 4 connected with a base, and a base connected between the PMOS transistor M 5 and the NMOS transistor M 3 , and the collector is a bipolar transistor connected to a power supply terminal V DD . Q 3 and a capacitor C 2 connected between the first transmission gate (X 1 ) and the bipolar transistor Q 3 . 제1항에 있어서, 상기 선택스위치(17)는 상기 홀드스위치(11)의 제1트랜스미션 게이트(X1)가 온되면 서로 접속하여 제1적분기(13)의 출력이 상기 궤환증폭기(15)에 인가되도록 하는 제3 및 제6트랜스미션 게이트(X3,X6)와, 상기 제2트랜스미션 게이트(X2)가 온되면 서로 접속하여 제2적분기(13')의 출력이 상기 궤환증폭기에 인가되도록 하는 제4 및 제5트랜스미션 게이트(X4,X5)를 구비하여 이루어지는 것을 특징으로 하는 트랙/홀더 회로.The method of claim 1, wherein the selection switch 17 to the first feedback amplifier 15 outputs the above-described transmission gate (X 1) is when the first integrator (13) connected to each other one of the hold switch 11 When the third and sixth transmission gates X 3 and X 6 and the second transmission gate X 2 are turned on, they are connected to each other so that the output of the second integrator 13 ′ is applied to the feedback amplifier. And a fourth and fifth transmission gate (X 4 , X 5 ). 제1항에 있어서, 제2적분기(13')는 제1적분기(13)와 동일하게 구성됨을 특징으로 하는 트랙/홀더 회로.2. Track / holder circuit according to claim 1, characterized in that the second integrator (13 ') is configured identically to the first integrator (13). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016831A 1993-08-27 1993-08-27 Track/holder circuit KR950013874B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930016831A KR950013874B1 (en) 1993-08-27 1993-08-27 Track/holder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016831A KR950013874B1 (en) 1993-08-27 1993-08-27 Track/holder circuit

Publications (2)

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KR950007300A true KR950007300A (en) 1995-03-21
KR950013874B1 KR950013874B1 (en) 1995-11-17

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KR1019930016831A KR950013874B1 (en) 1993-08-27 1993-08-27 Track/holder circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100976904B1 (en) * 2002-06-13 2010-08-18 스카이워크스 솔루션즈 인코포레이티드 Sequential dc offset correction for amplifier chain

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100976904B1 (en) * 2002-06-13 2010-08-18 스카이워크스 솔루션즈 인코포레이티드 Sequential dc offset correction for amplifier chain

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Publication number Publication date
KR950013874B1 (en) 1995-11-17

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