KR950012322B1 - Vc-4 mapping control unit in the physical layer of b-isdn - Google Patents

Abstract

The circuit is for generating position data of path overhead and control signals to control VC-4 projection and STM-1 flaming. The circuit comprises a control signal generator(21) for generating signals to control signal interface and VC-4 projection, an ATM cell control unit(22) for storing ATM cell and for generating cell reception start signal, and an odd parity signal generator(23) for generating odd parity signal by using control signal, data parity and cell reception start signal.

Description

Control device for VC-4 mapping at the physical layer of a broadband integrated information network (B-ISDN)

1 is a block diagram of a transmitter of a B-ISDN STM-1 physical layer.

2 is an overall configuration diagram of a VC-4 mapping control unit according to the present invention.

3 is a detailed block diagram of a control signal generator.

4 is a detailed block diagram of ATM cell storage and control logic.

5 is a detailed block diagram of an odd parity generation unit.

* Explanation of symbols for main parts of the drawings

21: control signal generator 22: ATM cell storage and control organization

23: odd parity generator

According to the present invention, when a physical layer transmits information in an STM-1 frame in an synchronous multi-hierarchy environment, a 53-byte ATM cell is used for a VC (Virtual Container) -4 page in a broadband integrated information network (B-ISDN). It relates to a VC-4 mapping control device that maps loads and generates control signals and information about the position of the passover head to enable fast and accurate STM-1 framing operation.

The idea of the ATM cell to C-4, recommended by CCITT, is to fill C-4 sequentially with ATM cells to be transmitted, rather than multiplexing each ATM cell to form a C-4 pairload. However, since the size of C-4 is not an integer multiple of an ATM cell, the boundaries of ATM cells in C4 do not exist at the same location. However, among the path overhead of the transmitted STM-1 frame, the H4 byte should have information about the offset from the header position of the first ATM cell after the self-space. Therefore, if this information is easily obtained and the location of other path overheads is known accurately, the processing delay for framing can be greatly reduced when 9 bytes of path overhead information are mapped to the STM-1 frame.

Accordingly, the present invention can provide the control signal required by the pass overhead information in connection with the mapping of the ATM cell within C-4, and also provide the odd parity for the data, thereby increasing the reliability of the data and the control signal. The purpose is to provide a control device for the VC-4 mapping.

In order to achieve the above object, the present invention matches the signal interface between the ATM cell generator and the STM-1 framing device and provides control signals (envelope, frame sync, VC4 envelope, C1J1, POH) for VC-4 mapping. ATM cell storage and control for generating a control signal generating means and a cell receiving start signal to the control signal generating means so as to receive and store an ATM cell and store the stored cells in synchronization with a control signal, and output data parity (DP). And an odd parity generating means for receiving an odd parity by receiving a control signal, a data parity, and a cell reception start signal from the control signal generating means and the ATM cell storing and controlling means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a transmitter of a B-ISDN STM-1 class physical layer to which the present invention is applied.

As shown in the figure, the VC-4 mapping controller 12 proposed by the present invention is located between the ATM cell generator 11 and the STM-1 framing unit 13 so that the ATM cell is an STM-1 frame. Supply the control signals needed to be mapped. Reference numeral 14 denotes a bit stream generator, and 15 denotes an E / O converter.

2 is an overall configuration diagram of the VC-4 mapping control device of the present invention.

Reference frame 21 is a frame that is a reference signal that can be considered and transmitted as a reference when an external device transmitting an ATM cell transmits a cell, that is, an envelope signal for C-4 and an 18 ms signal indicating a period of 125 ms The VC4 envelope signal required for VC-4 mapping by the function of generating a sink and the cell start signal, the pulse signal C1J1 indicating the position of the C1 and J1 bytes, and the POH (Path indicating the position of the path overhead). (22) A function to receive and store atm cells and to generate alarm signals, stop signal for cell reception, and to read data necessary for parity calculation from the buffer. ATM cell storage and control logic to perform such. Here, the write enable * signal may be generated by using the C4 envelope signal provided by 21 and maintaining activation 0 only for the transmission time of a valid ATM cell. Reference numeral 23 is an odd parity generator that provides odd parity values for all signals provided to an external STM-1 framing system.

3 is a detailed configuration diagram of the control signal generator 21.

When the VC-4 envelope generator 31 receives the cell reception start * signal, the VC-4 envelope generator 31 generates basic control signals for the STM-1 frame, that is, an R9 signal ALVC4 envelope signal having a frequency of 72 kHz. The R9 signal represents the boundary of each row of the STM-1 frame and the VC4 envelope signal is an envelope for 261 VC-4 payloads and remains zero for nine Saxony overhead positions. The C1J1 indication signal generator generates a 125 ms cycle based on the position of the C1, one of the section overhead bytes, and the first J1 byte transmitted from the pass-overhead, by the R9 signal received from the VC-4 envelope generator 31. Inform. Since the JI byte occurs in a fixed position, the C1J1 signal becomes 1 for only 2 clock cycles and remains 0 for the rest of the time. The POH indication signal generator 33 generates a POH signal indicating the position of the path overhead byte. The VC4 aligner 34 generates a VC4 envelope signal synchronized with the C1J1 and POH signals as a retiming unit. The reception control signal generator 35 generates a frame sync with C4, which is a sync signal having an 8 kHz frequency. By this signal, the external ATM cell generation device transmits the cell in accordance with the C4 signal by synchronizing the entire cycle of cell transmission to 125 sec. The frame sync and C4 signals are reference signals that may be used by an external device.

4 is a detailed block diagram of an ATM cell storage and control logic unit.

The ATM cell storage unit 41 stores cells received when the write enable * signal is zero. The write enable * signal may be a signal using the C4 signal provided from the reception control signal generator 35, or may be any signal that exists only for the 260-byte clock for the entire 270-byte clock periodically in the normal state.

The control logic 42 provides a read enable * signal and a read clock to the ATM cell storage 41 upon receiving the cell reception start * signal received from the ATM cell storage 41. The read enable * signal has 10 bytes deactivated 1 during clock time and activation 0 is repeated periodically for a 260 byte clock time. ATM cell storage 41 emits data DP by read enable * and read clock received from control logic 42 and generates alarm signals associated with the buffer.

It is also configured to generate a cell stop signal when an overflow occurs in the buffer due to an error operation of the system.

5 is a detailed configuration diagram of an odd parity generation unit.

The signal alignment unit 51 is a function unit for synchronizing the phases of the signals received from the C1J1 instruction signal generator 32, the POH instruction signal generator 33, and the VC4 aligner 34, and the data parity calculator ( 52 is a data parity calculation unit that initializes all information by the cell reception start * signal received from the ATM cell storage unit 41, receives data parity DP, and calculates even parity with respect to data. The odd parity calculator 53 receives C1J1, VC4, POH, and data parity from the signal sorter 51 and the data parity calculator 52 to generate odd parity.

Therefore, the present invention configured and operated as described above can reduce the delay required for STM-1 framing processing and make the WDJ of the cell easier by synchronizing the transmission data to the parity signal, and the external devices can be operated normally. It also provides a reporting function for errors when not in operation, which is a useful invention that can be used as a core device when the broadband integrated information communication room is configured as a physical layer in a synchronous multi-tier environment.

Claims (4)

Control signal generating means 21 for matching the signal interface between the ATM cell generator and the STM-1 framing device and generating control signals (envelope, framing, VC4 envelope, C1J1, POH) for VC-4 mapping. ATM cell storage and control means 22 for receiving and storing an ATM cell and providing a cell reception start signal to the control signal generating means 21 and outputting data parity DP so that the stored cell is synchronized with the control signal. And odd parity generating means 23 receiving control signals, data parity, and cell reception start signals from the control signal generating means 21 and the ATM cell storing and controlling means 22 and providing odd parity. VC-4 mapping controller, characterized in that. The control signal generating means (21) according to claim 1, wherein the control signal generating means (21) receives a cell reception start signal from the ATM cell storing and controlling means (22) and provides basic control signals (R9, VC4 envelope) for the STM-1 frame. A VC4 envelope generating means 31 for outputting a signal, a cell reception start signal from the ATM cell storing and controlling means 22, and an R9 signal from the VC4 envelope generating means 31 to generate a C1J1 indication signal. C1J1 indication signal generating means 32, a cell reception start signal from the ATM cell storage and control means 22, and a R9 signal from the VC4 envelope generating means 31; VC4 alignment means for receiving the cell reception start signal from the ATM cell storage and control means 22 and the VC4 envelope signal from the VC4 envelope generating means 31 and generating the VC4 envelope signal synchronized with the C1J1 and POH signals. 34, and the system clock Force receiving VC-4 mapping control apparatus comprising a reception control signal generating means 35 for generating a frame sync and C4. 2. The ATM cell storage and control means (22) according to claim 1, wherein the ATM cell storage and control means (22) comprises: an ATM cell storage means (41) for receiving and storing an ATM cell and outputting a cell reception start signal and data parity; And a control logic (42) for receiving a cell reception start signal from 41) and providing a read enable signal and a read clock to the ATM cell storage means (42). The method of claim 1, wherein the odd parity generating means (23) comprises: signal aligning means (51) for receiving C1J1, POH, and VC4 signals, which are outputs of the control signal generating means (21), for synchronizing and outputting phases; Data parity calculation means 52 for receiving the data parity DP and the cell reception start signal from the ATM cell storage and control means 22, calculating and outputting even parity for the data, and the signal alignment means 51; And an odd parity calculating means 53 for receiving phase-synchronized C1J1, POH, VC4 signals from the data parity calculating means 52, receiving data parity from the data parity calculating means 52, and calculating and generating odd parity for a received input. VC-4 mapping controller.