KR950010126A - Method for forming source / drain junction of semiconductor device - Google Patents

Method for forming source / drain junction of semiconductor device Download PDF

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Publication number
KR950010126A
KR950010126A KR1019930019239A KR930019239A KR950010126A KR 950010126 A KR950010126 A KR 950010126A KR 1019930019239 A KR1019930019239 A KR 1019930019239A KR 930019239 A KR930019239 A KR 930019239A KR 950010126 A KR950010126 A KR 950010126A
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KR
South Korea
Prior art keywords
ion implantation
junction
forming
semiconductor device
source
Prior art date
Application number
KR1019930019239A
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Korean (ko)
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KR970009277B1 (en
Inventor
유상호
나상군
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR93019239A priority Critical patent/KR970009277B1/en
Publication of KR950010126A publication Critical patent/KR950010126A/en
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Publication of KR970009277B1 publication Critical patent/KR970009277B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 소오스/드레인 접합부(Source/Drain Junction) 형성방법에 관하여 기술한 것으로, 특히 깊이가 얕은 소오스/드레인 접합부를 형성하기 위한 N+또는 P+형 불순물을 제2단계 이온주입공정으로 주입하되, 먼저 제1이온주입공정시 이온주입 에너지, 이온주입량 및 접합부의 깊이를 설정하여 공정을 실시하고, 이어서 제2이온주입공정을 상기 제1이온주입공정시의 조건과 같거나 조금 크게 설정하여 이온농도 분포의 꼬리 부분이 제1이온주입공정시 프로젝트 랜지(Projected Range)에 위치되도록 공정을 실시하고, 이후 급속열처리 및 접합부의 표면농도가 증대되어 표면의 접촉저항을 감소시키며, 접합부의 깊이를 얕게 형성시킬 수 있는 반도체 소자의 소오스/드레인 접합부를 형성하는 방법에 관하여 기술된다.The present invention relates to a method of forming a source / drain junction of a semiconductor device, and in particular, a second step of implanting an N + or P + type impurity for forming a shallow source / drain junction. In the first ion implantation process, the ion implantation energy, the ion implantation amount, and the depth of the junction portion are first set, and then the second ion implantation process is equal to or slightly larger than the conditions of the first ion implantation process. Setting the tail portion of the ion concentration distribution in the projected range during the first ion implantation process, and then increasing the surface concentration of the rapid heat treatment and the junction to reduce the contact resistance of the junction, A method of forming a source / drain junction of a semiconductor device capable of forming a shallow depth is described.

Description

반도체 소자의 소오스/드레인 접합부 형성방법Method for forming source / drain junction of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 및 제1B도는 본발명에 의한 반도체 소자의 소오스/드레인 접합부을 형성하는 단계를 설명하기 위해 도시한 단면도.1A and 1B are cross-sectional views illustrating the steps of forming a source / drain junction of a semiconductor device according to the present invention.

Claims (1)

반도체 소자의 소오스/드레인 접합부 형성방법에 있어서, 실리콘 기판(1)상에 필드 옥사이드(2), 게이트 옥사이드(3) 및 게이트 전극(4)을 형성한 상태에서, N+또는 P+형 불순물을 일정한 주입 에너지와 이온양으로 일정시간 이온 주입하는 제1이온주입공정으로 깊이가 얕으나 농도가 적은 상태의 소오스/드레인 접합부(6)를 형성하는 단계와, 상기 단계로부터 제1이온주입공정과 동일한 조건으로 제2이온 주입공정을 실시하여 상기 접합부(6)의 농도를 증가시키는 단계와, 상기 단계로부터 급속 열처리하고 이후 튜브 열처리하여 상기 접합부(6)를 완성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 소오스/드레인 접합부 형성방법.In a method of forming a source / drain junction of a semiconductor device, N + or P + type impurities are formed in a state where a field oxide 2, a gate oxide 3, and a gate electrode 4 are formed on a silicon substrate 1. Forming a source / drain junction 6 having a shallow depth but a low concentration in a first ion implantation process in which ion implantation is performed for a predetermined time with a constant implantation energy and an amount of ions; A semiconductor device comprising a step of increasing the concentration of the junction 6 by performing a second ion implantation process under conditions, and then completing the junction 6 by rapid heat treatment from the step and then tube heat treatment. A method of forming a source / drain junction of. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93019239A 1993-09-22 1993-09-22 Source/drain junction formation method of semiconductor device KR970009277B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93019239A KR970009277B1 (en) 1993-09-22 1993-09-22 Source/drain junction formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93019239A KR970009277B1 (en) 1993-09-22 1993-09-22 Source/drain junction formation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950010126A true KR950010126A (en) 1995-04-26
KR970009277B1 KR970009277B1 (en) 1997-06-09

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Application Number Title Priority Date Filing Date
KR93019239A KR970009277B1 (en) 1993-09-22 1993-09-22 Source/drain junction formation method of semiconductor device

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Publication number Priority date Publication date Assignee Title
KR100633184B1 (en) 2004-04-06 2006-10-12 엘지전자 주식회사 Method and apparatus for setting menu of an image display device

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