KR950009896A - Align key pattern of a semiconductor device and a method of forming the same - Google Patents

Align key pattern of a semiconductor device and a method of forming the same Download PDF

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Publication number
KR950009896A
KR950009896A KR1019930018129A KR930018129A KR950009896A KR 950009896 A KR950009896 A KR 950009896A KR 1019930018129 A KR1019930018129 A KR 1019930018129A KR 930018129 A KR930018129 A KR 930018129A KR 950009896 A KR950009896 A KR 950009896A
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KR
South Korea
Prior art keywords
field oxide
alignment
semiconductor substrate
pattern
oxide film
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KR1019930018129A
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Korean (ko)
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KR960016314B1 (en
Inventor
양원석
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김광호
삼성전자 주식회사
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Priority to KR1019930018129A priority Critical patent/KR960016314B1/en
Publication of KR950009896A publication Critical patent/KR950009896A/en
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Publication of KR960016314B1 publication Critical patent/KR960016314B1/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

본 발명은 반도체 장치의 얼라인 키 패턴(Align key pattern) 및 그 형성방법에 관한 것으로, 특히 노광공정에서 마스크와 반도체 기판상의 얼라인 패턴을 효과적으로 정준시키기 위한 큰 단차를 갖는 얼라인 키 패턴을 자기정합적으로 재형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment key pattern of a semiconductor device and a method of forming the same. In particular, an alignment key pattern having a large step for effectively leveling an alignment pattern on a mask and a semiconductor substrate in an exposure process is magnetized. It is about a method of reforming consistently.

즉, 본 발명에서는 반도체 장치의 절단선내의 얼라인 키로 쓰이는 필드산화막의 주변에 상기 필드산화막과 식각율이 크게 다른 다결정실리콘을 도포한 후, 상기 두 물질의 식각선택비의 차이를 이용하여 큰 단차를 갖는 얼라인 키 패턴을 자기정합적으로 형성할 수 있다. 또한, 콘택홀 형성시 충간절연막과 필드산화막의 낮은 선택비차이를 이용하여 급격한 단차를 갖는 얼라인패턴을 재형성할 수 있다.That is, in the present invention, after the polycrystalline silicon having a large etch rate different from that of the field oxide film is coated around the field oxide film used as the alignment key in the cutting line of the semiconductor device, a large step is obtained by using the difference in the etching selectivity of the two materials. It is possible to form an alignment key pattern having a self-alignment. In addition, when the contact hole is formed, an alignment pattern having a sharp step may be reformed by using a low selectivity difference between the interlayer insulating layer and the field oxide layer.

따라서, 이후의 공정에서 마스크 얼라인 시 오차를 줄일 수 있으며, 별도의 얼라인 키를 형성할 필요가 없게 된다.Therefore, an error in mask alignment may be reduced in a subsequent process, and it is not necessary to form a separate alignment key.

Description

반도체 장치의 얼라인 키 패턴(Align key pattern) 및 그 형성방법Align key pattern of a semiconductor device and a method of forming the same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도 내지 제8도는 본 발명에 의한 우수한 단차를 갖는 얼라인 키 패턴(Align key pattern)의 형성방법의 일실시예를 설명하는 반도체 장치의 단면도들이다.6 to 8 are cross-sectional views of a semiconductor device for explaining an embodiment of a method of forming an alignment key pattern having excellent step according to the present invention.

제9도는 본 발명에 의한 우수한 단차를 갖는 얼라인키 패턴의 형성방법의 또 다른 실시예을 설명하는 반도체 장치의 단면도이다.9 is a cross-sectional view of a semiconductor device for explaining another embodiment of the method for forming the alignment key pattern having the excellent step according to the present invention.

Claims (6)

반도체 기판의 절단선내에 돌출되어 형성된 얼라인키패턴; 및 상기 얼라인패턴의 주변을 따라 상기 얼라인키패턴과 단차를 이루며 형성된 홈을 구비하는 것을 특징으로 하는 반도체 장치.An alignment key pattern protruding from a cutting line of the semiconductor substrate; And a groove formed along the periphery of the alignment pattern to form a step with the alignment key pattern. 제1항에 있어서, 상기 얼라인키패턴의 필드산화막 및 그 하부의 반도체기판으로 구성된 것을 특징으로 하는 반도체 장치.2. The semiconductor device according to claim 1, comprising a field oxide film of said alignment key pattern and a semiconductor substrate below it. 반도체기판상에 필드산화막을 형성하는 단계; 결과물의 전면에 제1의 물질을 증착하여 제1의 물질층을 형성하는 단계; 상기 제1의 물질층의 일부를 제거하는 단계; 및 결과물의 전면에 제2의 물질을 증착한 후, 상기 필드산화막을 식각마스크로 하여 상기 필드산화막 및 그 주변의 상기 반도체기판위에 적층된 상기 제2의 물질층 및 상기 반도체기판을 순차적으로 이방성식각하여, 필드산화막 및 그 하부의 단차부로 구성된 얼라인패턴을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조방법.Forming a field oxide film on the semiconductor substrate; Depositing a first material on the front surface of the resultant to form a first material layer; Removing a portion of the first material layer; And depositing a second material on the entire surface of the resultant, and subsequently anisotropically etching the second material layer and the semiconductor substrate stacked on the field oxide film and the semiconductor substrate around the field oxide film as an etch mask. And forming an alignment pattern composed of a field oxide film and a stepped portion at a lower portion thereof. 제3항에 있어서, 상기 제1의 물질층을 형성하는 단계 이전에, 상기 필드산화막을 열적으로 성장시키는 단계; 및 상기 결과물의 전면을 에치백하여 상기 필드산화막 사이의 반도체 기판을 노출시키는 단계를 더 구비하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 3, further comprising: thermally growing the field oxide layer prior to forming the first material layer; And etching back the entire surface of the resultant to expose the semiconductor substrate between the field oxide films. 제3항에 있어서, 상기 제1의 물질층의 일부를 제거하는 단계는, 상기 제1의 물질층의 전면에 포토레지스트를 도포하는 단계; 결과물의 전면에 노광공정을 행함으로써 절단산부분을 제외하고 각셀 단위로 한정된 모양의 포토레지스트패턴을 형성하는 단계; 상기 포토레지스트패턴을 식각마스크로 이용하여 결과물전면에 이방성식각을 행함으로써, 상기 절단선부분의 제1의 물질을 제거하여 상기 필드산화막 및 그 주변의 반도체기판의 표면을 노출시키는 동시에 상기 절단선외의 제1의 물질층의 일부를 제거하여 각 셀 단위로 한정된 콘택트 홀을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 3, wherein removing a portion of the first material layer comprises: applying a photoresist to the entire surface of the first material layer; Forming a photoresist pattern having a shape defined by each cell except for the cutout portion by performing an exposure process on the entire surface of the resultant; By using the photoresist pattern as an etching mask, anisotropic etching is performed on the entire surface of the resultant to remove the first material of the cut line portion to expose the surface of the field oxide film and the semiconductor substrate in the vicinity thereof, And removing a portion of the first material layer to form a contact hole defined for each cell unit. 제3항에 있어서, 제1의 물질로는 산화물을 사용하고, 제2의 물질로는 다결정실리콘을 사용하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 3, wherein an oxide is used as the first material and polycrystalline silicon is used as the second material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930018129A 1993-09-09 1993-09-09 Align key pattern for semiconductor device and forming method of the same KR960016314B1 (en)

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KR1019930018129A KR960016314B1 (en) 1993-09-09 1993-09-09 Align key pattern for semiconductor device and forming method of the same

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KR950009896A true KR950009896A (en) 1995-04-26
KR960016314B1 KR960016314B1 (en) 1996-12-09

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