KR950009382B1 - Voice data recording/reproducing apparatus for reducing cylinder diameter in dat recorder - Google Patents

Abstract

The sound data recording/reproducing device in a digital audio tape recorder comprises a drum composed of an upper drum and a lower drum, a small-size motor for rotating the drum, a record/reproduction amplifier for amplifying the sound data, a phase synchronization loop for generating a reproduction data clock from the sound data reproduced by the record/reproduction amplifier and outputting the reproduction data clock and the reproduced sound data, a time base controller, a signal processor, and a memory.

Description

Voice data recording / playback device for reducing the diameter of cylinders in digital audio tape recorders

1 is a diagram showing a state in which a tape is wound on a drum included in a conventional digital audio tape recorder.

2 is a structural diagram of a drum according to the present invention.

3 is a view showing a state in which the tape wound on the drum according to the present invention.

4 is a block diagram of a digital audio tape recorder according to the present invention.

5 is a detailed configuration diagram of the TBC section 42 in the configuration of FIG.

6 is a timing diagram for voice data processed in each part of FIG.

* Explanation of symbols for main parts of the drawings

20, 21: 1st, 2nd head 24: Drum

40: recording and reproducing amplifier 41: phase locked loop (PLL)

42: Time Base Control (TBC) 43: Digital Signal Processor (DSP)

44 memory 45 analog-to-digital converter (ADC)

46: digital-to-analog converter (DAC) 50: multiplexer

51, 52: 1st, 2nd parallel circuit 53-56: 1st-4 buffer circuit

57, 58: 1st, 2nd parallel circuit 59: Demultiplexer

60: control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio tape recorder (hereinafter referred to as "R-DAT"), and more particularly, to an apparatus for allowing audio data to be normally recorded / reproduced even when the diameter of a cylinder is reduced.

A typical R-DAT mounts two heads in a cylinder (drum) having a diameter of 30 mm and helically scans each track of the tape to record audio data on the tape or to reproduce audio data recorded on the tape. In a conventional R-DAT for performing such an operation, a voice signal for recording is generally compressed and applied to a head mounted on a cylinder, and the voice data recorded in a compressed form on a tape is stretched and reproduced externally. A digital signal processor (hereinafter referred to as a "DSP") for transmitting as a voice signal is included, and a recording / reproducing amplifier connected between the DSP and the cylinder is included. At this time, the recording and reproducing recorder amplifies the audio data read out from the tape by the first head and the second head mounted on the cylinder and outputs the reproduced voice data, and amplifies the compressed voice data input for recording to record the recorded voice. Data is provided to the first head and the second head mounted to the cylinder.

In the conventional R-DAT configured as described above, the cylinder is normally standardized to have a diameter of 30 mm, and the DSP also has a standardized DSP suitable for a standard cylinder having a diameter of 30 mm.

However, in the conventional R-DAT as described above, when the tape is mounted on the deck, the height from the cassette to the upper drum is at least 30 mm due to the diameter of the drum, thereby miniaturizing the R-DAT. It was a big constraint. In addition, if only the diameter of the cylinder is small in the conventional R-DAT, the relative speed of the head and the tape is slowed down during recording and reproducing.

Accordingly, an object of the present invention is to provide a voice data recording / reproducing apparatus which employs a cylinder having a diameter smaller than that of a standard cylinder in R-DAT, and allows audio data to be normally recorded / reproduced even when a DSP for a standard cylinder is used. In providing.

Another object of the present invention is to provide a voice data recording / reproducing apparatus for realizing a portable R-DAT having a small size.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a view showing the configuration of a drum having a diameter (7.5 mm) of several times smaller than the standard diameter (30 mm) according to the present invention, the drum 24 according to the present invention, the voice signal on the lower peripheral wall surface The upper drum 22 having the first and second heads 20 and 21 symmetrically attached to each other in the radial direction, and the lower drum 23 having the same diameter as the upper drum to support the upper drum 22. Is structured as The drum 24 is connected to a small monitor 25 for rotating the drum 24.

3 is a diagram showing a state in which a tape is wound around the drum 24 according to the present invention, which is constructed as shown in FIG. 2.

4 is a diagram showing the configuration of the R-DAT according to the present invention. The R-DAT according to the present invention amplifies the audio data to be recorded and outputs the first and second heads 20 and 21 to the tape. And a reproduction data clock is generated from the recording and reproducing amplifier 40 which amplifies the audio data read out by the first and second heads 20 and 21, and the audio and data reproduced by the recording and reproducing amplifier 40. A phase locked loop 41 which outputs the reproduced data clock together with the reproduced voice data, and inputs the compressed voice data to be recorded together with the recorded data clock. The compressed audio data to be compressed is expanded on the basis of the data clock and output to the recording and reproducing amplifier 40, and the audio data and the reproduction data clock reproduced from the PLL 41 are input together to write the reproduction data clock. The time base control (TBC) 42 which compresses and outputs the reproduced voice data, and decompresses the compressed voice data from the TBC 42, followed by digital / analog processing. The audio data to be recorded is output to a converter (Digital / Analog Converter: hereinafter referred to as "DAC") 46 and input from an analog / digital converter (hereinafter referred to as "ADC") 45. DSP 43 for generating the compressed audio data and recording data clock which have been processed and outputting the generated compressed audio data and recording data clock to TBC 42, and the TBC 42 for DSP 43. And a memory 44 which temporarily stores the voice data to be processed when decompressing the compressed voice data to be inputted from the compressed data or the compressed voice data input from the PLL 41 to be temporarily stored.

FIG. 5 is a diagram showing the detailed configuration of the TBC 42 in the configuration of FIG. 4, and it can be seen that the memory 44 is connected.

Referring to FIG. 5, the TBC 42 inputs the compressed audio data from the DSP 43 to the first input terminal I1 during recording, and the second output terminal O2 of the PLL 41 during reproduction. A multiplexer 50 for inputting the read / reproduced voice data output from the second head 21 and a second voice for converting serial voice data input from the multiplexer 50 into parallel voice data. A system for inputting serial audio data read and reproduced by the parallel circuit 52 and the first head 20 output from the first output terminal O1 of the PLL 41 to convert the parallel audio data into parallel audio data. First and second parallel circuits 51, the first buffer circuit 53 for transmitting the voice data converted in parallel form by the first series and parallel circuits 51 to the memory 44, and the second series and parallel circuits 52. A second buffer circuit 54 for transmitting the voice data converted into parallel form to the memory 44 and the data read out from the memory 44 during writing. The first parallel serial circuit 57 converts the columnar audio data into serial audio data and outputs the same to the first input terminal I1 of the recording / reproducing amplifier 40, and is read out from the memory 44 and input. The voice read out from the memory 44 by being connected between the second parallel serial circuit 58 and the first parallel serial circuit 57 and the memory 44 for converting the parallel voice data into the serial voice data. The third buffer circuit 55 for transmitting data to the first parallel serial circuit 57 and the audio data read out from the second parallel serial circuit 58 and the memory 44 are transferred to the second parallel serial circuit 58. The fourth buffer circuit 56 to be transmitted and the audio data of the serial type input from the second parallel series circuit 58 are transmitted to the second input terminal I2 of the recording / reproducing amplifier 40 at the time of recording, and at the time of reproduction. The demultiplexer 59 transmits to the first input terminal I1 of the DSP 43 and the recording data clock input from the DSP 43 during recording. While controlling the lexer 50 and the demultiplexer 59, the first and second parallel circuits 51 and 52, and the first and second parallel circuits 57 and 58 and the first to fourth buffer circuits 53 to 56, Accessing the memory 44 to expand the compressed voice data input from the DSP 43 to output to the recording and playback amplifier 40, the multiplexer 50 on the basis of the playback data clock input from the PLL (41) during playback And the memory 44 while controlling the demultiplexer 59, the first and second parallel circuits 51 and 52, and the first and second parallel circuits 57 and 58 and the first to fourth buffer circuits 53 to 56. ) And a control circuit section 60 for compressing the reproduced audio data input from the PLL 41 and outputting the compressed audio data to the DSP 43.

FIG. 6 is a diagram illustrating timings of signals processed in respective parts of FIG. 5. When FIG. 6 is neglected, the PHS is a head switching signal during reproduction, and the PED is a first parallel circuit 51 during reproduction. Is a reproduced voice data inputted to the second parallel circuit 52 during reproduction, and a PPD is compressed reproduced voice data output from the second parallel serial circuit 58 upon reproduction. to be.

Also referring to FIG. 6, WHS is a head switching signal during recording, WPA is compressed voice data input to the second serial-parallel circuit 52 during recording, and WFD is the first parallel serial circuit 57 during recording. Is the decompressed audio data outputted from the WSD, and the WSD is the decompressed audio data outputted from the second parallel serial circuit 58 at the time of recording.

Hereinafter, voice data reproduction and recording operations performed in the R-DAT according to the present invention will be described in detail with reference to FIGS. 2 to 6 as described above.

First, referring to FIG. 2, it can be seen that the drum 24 according to the present invention has only the diameter thereof reduced compared to the conventional drum and is identical in structure to the conventional drum. At this time, since the small motor 25 connected to the drum 24 rotates by an azimuth angle based on the rotation speed and the axis, the first and second heads 20 and 21 helically scan each track of the tape. . 3 is a view showing a state in which a tape is wound around a drum 24 structured as shown in FIG. 2, and the tape wraps around the drum's circumferential surface by 360 degrees.

Referring to FIG. 4, while reproducing and recording voice data, the following is performed.

First, the operation of the R-DAT when reproducing voice data will be described.

During reproduction, the recording and reproducing amplifier 40 amplifies the audio data reproduced by the first and second heads 20 and 21 at a predetermined amplification rate as the drum 24 as shown in FIG. 2 rotates. Output to PLL 41 via (O1, O2). The PLL 41 detects the rising edge and the falling edge of the reproduced voice data input from the first and second output terminals O1 and O2 of the recording and reproducing amplifier 40 to the first and second input terminals I1 and I2. Thereby generating a reproduction data clock, and outputting the generated reproduction data clock to the first to third output terminals O1, O2, and O3 together with the reproduced audio data input to the first and second input terminals I1 and I2. do. At this time, reproduced audio data is output to the first and second output terminals O1 and O2 of the PLL 41, and a reproduction data clock is output to the third output terminal O3.

Then, the TBC (receiving the reproduced audio data and the reproduction data clock outputted from the first to third output terminals O1, O2 and O3 of the PLL 41 through the first to third input terminals I1, I2 and I3) 42 accesses the memory 44 based on the reproduction data clock, stores and reads the reproduced voice data in the memory 44 for a predetermined time, and generates compressed voice data to generate a first input terminal of the DSP 43. Provided by (I1).

As a result, the DSP 43 processes the audio data compressed and input by the TBC 43 and outputs it to the DAC 46 so that the reproduced audio signal is transmitted to the outside.

Next, the operation of the R-DAT for recording the audio signal will be described.

The audio signal for recording input from the outside is applied to the ADC 45, converted into voice data, and provided to the second input terminal I2 of the DSP 43. The DSP 43 processes the voice data to generate compressed voice data and a recording data clock, and generates the compressed voice data and the recording data clock through the first and second output terminals O2 and O3, respectively. 42) to the fourth and fifth input terminals I4 and I5.

Then, the TBC 42 accesses the memory 44 based on the recording data clock, stores and reads the compressed voice data in the memory 44 for a predetermined time, and expands the compressed voice data, thereby expanding the compressed voice data. Is applied to the first and second input terminals I1 and I2 of the recording / reproducing amplifier 40 through the first and second output terminals O1 and O2.

As a result, the recording / reproducing amplifier 40 for inputting the voice data extended by the TBC 42 first or second head 20 to helically scan each track of the tape by rotating the drum 24. Record audio data on a tape.

Finally, the operation of the TBC 43 which expands the compressed voice data at the time of recording and compresses the voice data at the time of reproduction is shown in FIG. 5 showing the detailed configuration of the TBC 43 and the timing of the signals processed at this time. It demonstrates with reference to FIG.

First, the operation during reproduction will be described.

신호를 발생한다.During playback, the first head 20 reads and reproduces the audio data of the PHD of FIG. 6 from the tape according to the head switching signal of the PHS of FIG. 6, and the second head 21 of the PSD of FIG. Read and play back voice data in the form The read and reproduced voice data are applied to the first input / parallel circuit 51 and the second input terminal I2 of the multiplexer 50 via the recording / reproducing amplifier 40 and the PLL 41, respectively. At this time, the reproduction data clocks generated by the PLL 41 are respectively applied to the second input terminal I2 of the control circuit unit 60 through the line 9. Then, the control circuit unit 60 generates the first, second, and fourth latch signals, the mode control signal, and the transmission / reception clock based on the reproduction data clock input to the second input terminal I2. Sequential address and lead / light bar for access

Generate a signal.

The multiplexer 50 selects the second input terminal I2 in accordance with the mode control signal applied from the control circuit unit 60 to output the reproduced voice data output from the second output terminal O2 of the PLL 41. After receiving through 3) and outputs to the second serial-parallel circuit (52). Whenever the reception clock is applied from the control circuit unit 60, the second serial parallel circuit 52 receives serially reproduced audio data such as PSD of FIG. When data is input, the audio data of a predetermined bit is output to the second buffer circuit 54 as the second reproduction audio data by the second latch signal applied from the control circuit unit 60.

On the other hand, the first series-parallel circuit 51 and the PFD of FIG. 6 applied from the first output terminal I1 of the PLL 41 through the line 1 each time the reception clock is applied from the control circuit 60 and When the voice data of the same serial type is input by 1 bit and the voice data of a predetermined bit is input, the first buffer circuit converts the voice data of a predetermined bit as the first reproduction voice data by the first latch signal applied from the control circuit unit 60. Output to 53.

Then, the first buffer circuit 53 latches the output of the first serial-parallel circuit 51 by the first latch signal applied from the control circuit unit 60, thereby bus-loading the first reproducing audio data latched. The second buffer circuit 54, which is stored in the memory 44 through the first buffer circuit 53 and alternately operates with the first buffer circuit 53, is connected to the second serial parallel circuit by a second latch signal applied from the control circuit unit 60. The output of 52 is latched to store the latched second reproduction audio data in the memory 44 via the bus line 4.

On the other hand, the fourth buffer circuit 56 latches the reproducing voice data read out from the memory 44 and output through the bus line 4 by the fourth Rachae signal applied from the control circuit unit 60 to perform the second parallel series. Output to the circuit 58. Then, the second parallel circuit 58 receives the output of the fourth buffer circuit 56 by the fourth latch signal applied from the control circuit unit 60, and each time a transmission clock is applied from the control circuit unit 60. By outputting the output of the input fourth buffer circuit 56 to the demultiplexer 59 by 1 bit, the audio data in the compressed form as shown in FIG. 6 PPD is output.

Then, the demultiplexer 59, which selects the second output terminal O2 at the time of reproduction by the mode control signal applied from the control circuit unit 60, receives the compressed voice data output from the second parallel serial circuit 58. Output to the second output terminal (O2). Accordingly, the compressed voice data is transmitted to the first input terminal I1 of the DSP 43 through the line 7.

In this case, the control circuit unit 60 generates a transmission clock having a predetermined cycle smaller than the reception clock cycle so that the reproduced voice data transmission time is two times shorter than the first and second reproduction voice data input time, thereby accumulating data. .

Next, the operation at the time of recording will be described.

신호를 또한 발생한다.During recording, the DSP 43 outputs the compressed audio data through the line 2, and outputs the recording data clock through the line 8. Then, the control circuit unit 60 for inputting the recording data clock to the first input terminal I1 through the line 8 generates the second to fourth latch signals, the mode control signal and the transmission and reception clocks based on the recording data clock. Sequential address and read / write bar for accessing the memory 44

It also generates a signal.

At this time, the multiplexer 50 receives the compressed recording audio data from the line 2 by selecting the first input terminal I1 according to the mode control signal applied from the control circuit unit 60, and the second serial parallel circuit 52. Will output Then, whenever the receiving clock is applied from the control circuit unit 60, the second serial circuit 52 receives one bit of compressed audio data in series, such as WPS of FIG. 6, from the multiplexer 50. When the recording audio data of the bit is input, the recording audio data of the predetermined bit is output to the second buffer circuit 54 by the second latch signal applied from the control circuit unit 60. Then, the second buffer circuit 54 latches the output of the second series-parallel circuit 52 whenever the second latch signal is applied from the control circuit unit 60 and stores the output in the memory 44 through the bus line 4. do.

On the other hand, the third buffer circuit 55 receives the recording voice data read out from the memory 44 by the third latch signal applied from the control circuit unit 60 through the bus line 4, the first parallel series circuit ( 57 latch, and the fourth latch circuit 56, which is sequentially operated with the third latch circuit 55, is read from the memory 44 by the fourth latch signal applied from the control circuit unit 60. The voice data is input through the bus line 4 and latched to the second parallel serial circuit 58. At this time, the first parallel serial circuit 57 inputs the recording audio data output from the third latch circuit 55 by the third latch signal applied from the control circuit unit 60, and inputs the input recording audio data to the control circuit unit. Each time a transmission clock is applied from 60, the first recording audio data in the form of WFD shown in FIG. 6 is outputted by one bit to the first input terminal I1 of the recording / reproducing amplifier 40 through the line 5. Occurs.

On the other hand, the second parallel series circuit 58 inputs the recording audio data output from the fourth buffer circuit 56 by the fourth latch signal applied from the control circuit unit 60, and inputs the input recording audio data. Each time a transmission clock is applied from the control circuit section 60, the output signal is decoded one bit to the demultiplexer 59 to generate second recording audio data such as the WSD shown in FIG. At this time, the demultiplexer 59 selects the first output terminal I1 according to the mode control signal applied from the control circuit unit 60 so that the second recording voice data applied from the second parallel series circuit 58 is line 6. Through this, it is output to the second input terminal I2 of the recording / reproducing amplifier 40.

In this case, the control circuit unit 60 expands the compressed recording audio data by the period of the reception clock being predetermined times faster than the period of the transmission clock and the period of the second latch signal being predetermined times faster than the periods of the third and fourth latch signals. Can be printed.

As described above, the present invention has the advantage of providing an R-DAT that is easy to miniaturize and carry, since the voice information can be recorded and reproduced normally even when the diameter of the cylinder is reduced.

Claims (2)

A digital audio tape recorder comprising: an upper drum (22) having radially symmetrically attached first and second heads (20, 21) for recording and reproducing an audio signal on a lower circumferential wall; A drum 24 having a diameter having a diameter several times smaller than a standard diameter, the lower drum 23 having a diameter equal to the diameter of the upper drum 22 for supporting; A small motor 25 for rotating the drum 24; By amplifying the voice data to be recorded and outputting them to the first and second heads 20 and 21, the voice data is recorded on the tape, and the voice data read by the first and second heads 20 and 21 are amplified. A recording / reproducing amplifier 40; A phase locked loop (41) for generating a reproduction data clock from the audio data reproduced by the recording and reproduction amplifier (40), and outputting the reproduction data clock together with the reproduced audio data; The compressed audio data to be recorded is input together with the recording data clock to expand the compressed audio data to be recorded based on the recording data clock, and output the compressed audio data to the recording / playback amplifier 40. A timebase control (42) for compressing the reproduced voice data output from the PLL (41); The audio data compressed by the timebase control 42 is expanded to be output as a reproduction signal, the input recording signal is compressed and converted into compressed audio data, and output to the timebase control 42. Signal processing means for outputting voice data and generating a recording data clock from the recording signal and outputting the recording data clock to the timebase control 42; The voice data processed when the timebase control 42 decompresses the compressed voice data to be recorded input from the signal processing means or compresses the reproduced voice data input from the phase-locked loop 41. And a memory (44) for temporarily storing the voice data recording / reproducing apparatus. 2. The phase locked loop according to claim 1, wherein the time base control (42) inputs the voice data compressed from the signal processing means to the first input terminal (I1) at the time of recording the voice data, and at the time of reproducing the voice data. A multiplexer (50) for inputting audio data read and reproduced by the second head (21) output from the second output terminal (O2) of (41); A second serial-parallel circuit 52 for converting serial speech data input from the multiplexer 50 into parallel speech data; First serial parallel circuit 51 for inputting and converting serial audio data read and reproduced by the first head 20 output from the first output terminal O1 of the PLL 41 into parallel audio data. )Wow; A first buffer circuit (53) for transmitting voice data converted in parallel form by the first serial-parallel circuit (51) to the memory (44); A second buffer circuit (54) for transmitting the voice data converted in parallel form by the second serial and parallel circuit (52) to the memory (44); A first bottle for converting parallel voice data, which is read out from the memory 44 and inputted, into voice data in serial form when the voice data is recorded, and outputting the same to the first input terminal I1 of the recording / reproducing amplifier 40. A series circuit 57; Between the second parallel serial circuit 58 and the first parallel serial circuit 57 and the memory 44 for converting parallel speech data read out from the memory 44 into serial speech data. A third buffer circuit 55 connected to the first buffer circuit 55 for transmitting audio data read out from the memory 44 to the first parallel serial circuit 57; A fourth buffer circuit 56 connected between the second parallel serial circuit 58 and the memory 44 to transmit voice data read out from the memory 44 to the second parallel serial circuit 58; ; When the audio data is recorded, the serial audio data input from the second parallel serial circuit 58 is transmitted to the second input terminal I2 of the recording / reproducing amplifier 40, and the signal processing is performed when the audio data is reproduced. A demultiplexer (59) for transmitting to the means; The multiplexer 50, the demultiplexer 59, the first and second parallel circuits 51 and 52, and the first and second bottles on the basis of a recording data clock input from the signal processing means when recording voice data. By accessing the memory 44 while controlling the serial circuits 57 and 58 and the first to fourth buffer circuits 53 to 56, the compressed audio data input from the signal processing means is expanded to expand the recording / reproducing amplifier ( 40, the multiplexer 50, the demultiplexer 59, and the first and second parallel circuits 51, based on the reproduced data clock inputted from the phase-locked loop 41 when audio data is reproduced. 52) the memory 44 is accessed from the phase locked loop 41 while controlling the first and second parallel circuits 57 and 58 and the first to fourth buffer circuits 53 to 56. Compressed audio data is compressed to the signal processing means. Audio data recording / reproducing apparatus characterized in that it consists of a control circuit 60 for output.

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