KR950006570B1 - Rate matching and mux/demux controller of full electronic switching system - Google Patents

Abstract

The controller improves the efficiency of network cross link by variation of asynchronous communication function. The device includes a packet call control unit(1), a packet bus unit(2), a packet processing unit(3), and the packet assembly/division unit(4). The controller also includes a speed variation and multiple/reverse-multiple means(7) which transfers the output data, an asynchronous communication means(8) which divides the data to the subscriber, a common memory(11) which inputs the character information, a packet assemble/disassemble controller(5), an HDLC communication means(9) which interfaces to the common memory(11), and a control means(10) which has a microprocessor and a control program.

Description

Speed Matching and Multiple / Demultiplex Controller of Electronic Switch

1 is a block diagram of a packet switching device.

2 is a block diagram of the packet assembly / disassembly device.

3 is a schematic diagram of speed matching and multiple / demultiplexing controller of the present invention.

4 is a control flowchart of the control unit.

* Explanation of symbols for the main parts of the drawings

1: Packet call control device 2: Packet bus device

3: packet processing device 4: packet assembling / disassembling device

5: Packet assembly / disassembly controller 6: Speed matching and multiple / demultiplex controller

7: speed conversion and multiple / demultiplexer 7A: to

7N: Speed conversion and multiple / demultiplexer 8: Asynchronous communication unit

8A: to 8N: Asynchronous Communicator

9: HDLC communication unit 10: control unit

11: common memory

The present invention relates to a speed matching and multiple / demultiplex controller implemented in a packet testicular device in an electronic switchboard.

Speed matching and multiple / demultiplexing functions are applied to various fields such as interworking between networks with different data transmission rates or to receive services from a newly established network using existing terminals. there was.

The present invention devised to solve the above problems is that when the data inputted by the character data terminal subscribers accommodated in the public telephone network are multiplexed at the standard speed in the transitional state before the comprehensive information communication network is completely established, the data are inputted from the public telephone network. It is an object of the present invention to provide a matched multiplexing and multiplexing / demultiplexing controller which converts at the same rate as one speed and performs asynchronous communication function for each subscriber.

Accordingly, in order to achieve the above object, the present invention provides a packet call control device for receiving path information related to a packet call through an interconnection network between processors, and is connected to the packet call control device so as to facilitate smooth data collisions between devices in a packet switching device. A packet bus device that performs an arbitration function for communication, and is connected to the packet bus device to receive link establishment / release information from the packet call control device through the packet bus device, and to exchange packet data between originating and called parties. Packet assembling / disassembly, which connects to a packet processing device and the packet bus device, accepts a link connected to an external switch device, and assembles a character input from a public telephone network subscriber into a packet and decomposes the packet into characters. It is characterized by having a device.

Hereinafter, with reference to the accompanying drawings will be described in detail.

FIG. 1 is a block diagram of a packet switching device of an electronic switching system, in which 1 is a packet call control device, 2 is a packet bus device, 3 is a packet processing device, and 4 is a packet assembly / decomposition device.

Specifically, the packet switching device 1 comprising the above elements receives the packet information related to the packet call through the interconnection network between the processors, and transmits the packet processing device 3 through the packet bus device 2. The link setting / release information is provided, the billing information related to the packet call is requested from the packet processing apparatus 3, the result is collected, configured in a desired form, and transmitted through the interconnection network between the processors.

The packet bus device 2 performs an arbitration function for smooth communication without data collision between the devices in the packet switching device.

The packet bus device 3 receives control information from the packet call control device 1 through the packet bus device 2 by receiving a link connected to an external switch device, and transmits packet data between the calling / receiving side. Replace it.

The packet assembling / decomposing device 4 performs a function of assembling a character input from a public telephone network subscriber into a packet by receiving a link connected to an external switch device and decomposing the packet into characters.

2 is an internal configuration diagram of the packet assembling / disassembling apparatus 4 incorporating the present invention, where 5 is a packet assembling / disassembly controller, and 6 is a speed matching and multiple / demultiplexing controller, respectively.

At least one speed matching and multiplex / demultiplexing controller 6 and packet assembly / disassembly controller 5, when physically connected, send and receive data, clock information, and a reset signal.

Packet assembling / decomposing device 4 performs CCITT X.3, X.28 and X.29 functions to provide packet services for character data terminals housed in public telephone networks. The data generated from the subscriber is multiplexed at the standard speed through the switch device, and the speed converting and multiplexing / demultiplexing controller 6 performs a function of converting and multiplexing / demultiplexing the input data at the original speed, and at the original speed. And a packet assembly / decomposition controller 5 having a function of assembling the converted data into packet data and decomposing the packet data to transmit the received data at the same speed as the character data terminal subscriber.

3 is a detailed configuration of the speed matching and multiple / reverse multiplexing controller 6 of the present invention, 7 is a speed conversion and multiple / demultiplex, 7a to 7n is a speed conversion and multiple / demultiplexer, 8 is asynchronous Communication units, 8a to 8n denote asynchronous communication units, 9 denotes HDLC communication units, 10 denotes a control unit, and 11 denotes a common memory.

Data input by asynchronous terminal subscribers accommodated in a public telephone network is multiplexed at a standard speed (6 Kbps) and input to a packet assembly / decomposition device 4 through a switch device.

The data entered in this manner is 1.2Kbps or 2.4Kbps, which is the same speed as the speed entered by the speed matching and multiplex / demultiplexer 6 in the packet assembling / decomposing device 4 and accommodated in the public telephone network. It is converted per subscriber.

This function is achieved through speed matching and speed conversion of the multiplex / demultiplexer 6 and the multiplex / demultiplexer 7 and the asynchronous communication section 8.

The speed converted input data is classified for each subscriber by the control unit 10 and the asynchronous communication unit 8, and a part of packet assembling function (limited packet assembling function) is imposed on each character type information and input to the common memory 11. The asynchronous communication section 8 here also has the same number of asynchronous communicators 8a to 8n as the speed conversion and multiple / demultiplexers 7a to 7n in the speed conversion and multiplex / demultiplexer 7.

On the other hand, the limited packet assembly and disassembly function is imposed so that the data input to the common memory 11 is transmitted to the packet assembly / disassembly controller 8 by the HDLC communication unit 9 in a transparent manner according to the command of the controller 10. Receive packet service.

The control unit 10 functions to control the overall, such as to impose a limited packet assembly function to the input character information.

The HDLC communication unit 9 transmits the character information to which the limited packet assembling function imposed in the common memory 11 is applied to the packet assembling / decomposing controller 5 according to the command of the controller 10.

4 is a process flow chart according to the control operation of the control unit 10. FIG. 4A is a process flow chart of the speed matching and demultiplexing functions, and FIG. 4B is a process flow chart of the speed matching and multiplexing functions.

First, the processing procedure of the speed matching and demultiplexing function by initializing 20 through FIG. 4A will be described as follows.

The controller 10 is prepared (30), and it is checked whether the asynchronous communication unit 8 requests an interrupt from the controller 10 (40). If there is no interrupt request, the process returns to the ready state 30. If there is an interrupt request, speed conversion and demultiplexing are performed to separate input information for each subscriber (50).

The packet separated information for each subscriber is purely packetized and stored in the common memory 11 (60), and the packet assembly and decomposition controller 5 stores the purely packetized subscriber-specific information stored in the common memory 11 through the HDLC communication function. Transmit (70).

After the transfer of information, the asynchronous communication unit 8 checks whether there is an interruption to the control unit 10 (80). If there is an interrupt request as a result of the investigation, the process returns to the process 50 to be separated for each subscriber, and if there is no interrupt request, the process returns to the process 30 in a ready state.

Next, referring to the speed matching and multiplexing related processing procedure through FIG. 4B, it is initialized (90), the controller 10 is prepared (100), and there is an interrupt request from the HDLC communication unit 9 to the controller 10. Investigate (10).

If there is no interrupt request as a result of the investigation, the control unit 10 returns to the ready state, and if there is an interrupt request, pure packet information is decomposed to form character information (120).

Next, the generated character information is stored in the common memory 11 (130). The subscriber loss character type information stored in the common memory 11 is matched and multiplexed through the asynchronous communication unit 8 to the switch device (140). After the transfer to the switch device is finished, whether or not there is an interrupt request from the HDLC communication unit 9 to the control unit 10 is checked (150).

If there is an interrupt request as a result of the investigation, the process returns to the process 120, and if there is no interrupt, the process returns to the process 100 and repeats the processing.

Looking at the detailed configuration of each functional unit operating as described above, each speed conversion and multiple / demultiplexer (7a to 7n) and each asynchronous communication device (8a to 8n) is implemented by Siemens ISDN Terminal Adapter Circuit (ITAC) IC It was.

The control unit 10 is implemented by Motorola's MC68000 series of processors, and the common memory 11 is composed of static random access memory (SRAM) to control the control unit 10, an ITAC IC (for example, 7a and 8a, or 7b). 8b ……) and the HDLC communication unit 9 are implemented to be shared.

The HDLC communication unit 9 is composed of SGS Thomson's MK5025 (X.25) IC.

Accordingly, the present invention, which is configured and operated as described above, performs speed conversion and multiplex / demultiplexing of data of asynchronous terminal subscribers of a public telephone network multiplexed at a standard speed inputted through a switch device in the ISDN when the public telephone network and the ISDN interoperate. Through the function, the subscribers accommodated in the public telephone network can be converted to each subscriber at the same speed as the input speed and can be individually processed through the asynchronous communication function, thereby enabling efficient interworking between the networks.

Claims (1)

Speed to be applied to the packet assembling / decomposing device 4 of the packet switching device including the packet call control device 1, the packet bus device 2, the packet processing device 3, and the packet assembling / decomposing device 4 In the matching and multiple / demultiplexing controller, connected to an external switch device, the asynchronous terminal subscribers accommodated in the public telephone network convert the data inputted by the subscriber at the same speed as the input rate, and multiplex it, and output it to the external switch device. Speed conversion and multiplexing / demultiplexing means (7) for demultiplexing and transferring data, asynchronous communication means (8) for separating data to be transmitted by subscribers through the speed conversion and multiplexing / demultiplexing means (7), The common memory 1 which imposes and inputs some packet assembly functions for each of the character information classified for each subscriber through the speed converting / multiplexing / demultiplexing means 7 and the asynchronous communication means 8. 1) and the data stored in the common memory 11 are transmitted to the packet assembly / decomposition controller 5 in a transparent manner, and the data input from the packet assembly / decomposition controller 5 is transferred to the common memory 11. Data input / output connected to the HDLC communication means 9 for interfacing, the speed conversion and multiplexing / demultiplexing means 7, the asynchronous communication means 8, the common memory 11, and the HDLC communication means 9 And a control means (10) comprising a microprocessor and a control program to control the multiplexing and demultiplexing of the electronic switch.