KR950005644B1 - Packet assembling and disassembling controller of full electronic switching system - Google Patents

Abstract

he controller that implements the packet assemble/disassemble function of switch exactly the same as the packet processing equipment. In the public switched telephone network, the controller provides an asynchronous terminal subscriber with the packet data services because it does not use extra interface function. The controller consists of a packet control equipment(1), a packet bus equipment(2), a packet processing equipment(3) and a packet assemble/disassemble equipment(4).

Description

Packet Assembly and Disassembly Controller of Electronic Switching System

1 is a block diagram of a packet switching device.

2 is a block diagram of a packet assembly and disassembly apparatus.

3 is a block diagram of a packet assembly and disassembly controller of the present invention.

4 is a flowchart of a controller of the present invention.

* Explanation of symbols for main parts of the drawings

1: packet call control device 2: packet bus device

3: packet processing device 4: packet assembling / disassembling device

5: Packet assembly / disassembly controller 6: Speed matching and multiple / demultiplex controller

7: HDLC matcher 7A to 7N: HDLC matcher

8 common memory 9 control unit

10: packet bus matching unit 10a and 10b: packet bus matching

The present invention relates to a packet assembly / disassembly controller implemented in a packet switching device in an electronic switchboard.

A packet is a block of data made according to a predetermined format after dividing a message into a predetermined number of bits for the purpose of transmission. Packet exchange is a packet exchange device that selects an appropriate communication path according to a destination address. This is how you send it. Packet exchanges do not accumulate messages, resulting in low response delays, and because of the limited length of data units, packets are not usually in files. By the way, although the data communication service is provided through the existing public telephone network, the public telephone network was originally designed to transmit voice, so there are many problems in transmitting data used by the computer at high speed. With the realization of the information communication network, the public telephone network and the packet switching network are integrated into the integrated information communication network so that voice / non-voice service can be provided through one network. Before the comprehensive telecommunication network is completely established, the public telephone network can be combined with the comprehensive telecommunication network to receive packet services, and then assemble the packet into a packet service. However, the conventional packet assembly disassembly function has a problem in that a function of interfacing at the exchange is configured by a separate module.

The present invention devised to solve the above problems, the packet assembly / disassembly function in the electronic switchboard to configure the same as the packet processing device to be installed in the packet switching device, so that no separate interface function is required, a comprehensive information communication network is completely constructed Its purpose is to provide packet data services efficiently by assembling text information into packets and decomposing the packet information into text information to an asynchronous terminal subscriber housed in a public telephone network.

Accordingly, in order to achieve the above object, the present invention provides a packet call control device for receiving path information related to a packet call through an interconnection processor-to-processor network, and is connected to the packet call control device so as to provide a smooth data collision between devices in a packet switching device. A packet bus device that performs an arbitration function for communication, and is connected to the packet bus device to receive link establishment / release information from the packet call control device through a packet bus device. A packet processing device for exchanging packet data between the calling / receiving side, and a function connected to the packet bus device and accommodating a link connected with a switch device to assemble a character input from a subscriber of a public telephone network into a packet; And a packet assembling / disassembling device for disassembling.

Hereinafter, with reference to the accompanying drawings will be described in detail.

FIG. 1 is a configuration diagram of a packet switching device of an electronic switching system, in which 1 is a packet call control device, 2 is a packet bus device, 3 is a packet processing device, and 4 is a packet assembling / decomposing device, respectively.

In detail, the packet switching device 1 including the above elements receives the packet information related to the packet call through the inter-processor interconnection network and transmits the packet processing device 3 through the packet bus device 2. The link setting / release information is provided, the collection of billing information related to the packet call is requested from the packet processing apparatus 3, the result is collected, configured in a desired form, and then transmitted through the interconnection network between processors.

The packet bus device 2 performs an arbitration function for smooth communication without data collision between devices in the packet switching device.

The packet processing device 3 receives control information from the packet call control device 1 through the packet bus device 2 by receiving a link connected to an external switch device, and transmits packet data between the originating / receiving side. Replace it.

The packet assembling / decomposing device 4 accommodates a link connected to an external switch device to assemble a character input from a public telephone network subscriber into a packet and to decompose the packet into characters.

2 is an internal configuration diagram of the packet assembling / disassembling apparatus 4 incorporating the present invention, where 5 is a packet assembling / disassembly controller, and 6 is a speed matching and multiple / demultiplexing controller, respectively.

At least one or more speed matching and multiplex / demultiplexing controllers 6 and packet assembly / disassembly controllers 5 are physically connected and send and receive data, clock, alarm, and reset signals.

Packet assembling / disassembling device 4 performs CCITT X.3, X.28 and X.29 functions to provide packet services for character data terminals housed in public telephone networks. For these functions, character data terminals of public telephone networks The data generated from the subscriber is multiplexed at a standard speed through an external switch device, and the speed conversion and multiplexing / demultiplexing controller 6 performs a function of converting and multiplexing / demultiplexing the input data at the original speed, and It consists of a packet assembly / decomposition controller 5 having a function of assembling the data converted at the rate into packet data and decomposing the packet data to transmit the received data at the same speed as the character data terminal subscriber.

3 is a detailed block diagram of the packet assembly / disassembly controller 5 of the present invention, wherein 7 is a High Level Data Link Control (HDLC) matching unit, 7a to 7n is an HDLC matching unit, 8 is a common memory, and 9 is a control unit. 10 denotes a packet bus matcher, and 10a to 10b denote packet bus matchers, respectively.

The information input from the speed matching and multiplexing / demultiplexing controller 6 is completely packetized by adding a header including various information through the HDLC matching unit 7 and the control unit 9 as a common memory (SRAM). (8).

The stored packet data is connected to the packet bus device 2 through a packet bus matching unit 10 which is operated in a redundant manner to improve data transmission reliability according to a command of the control unit 9, and the packet processing in which the other subscriber is connected. The data transmission from the X.25 terminal subscriber accommodated in the integrated information communication network to the asynchronous text terminal subscriber accommodated in the public telephone network is performed in the reverse order as described above, after the packet information is decomposed, the asynchronous terminal accommodated in the public telephone network. Only the data packetizing the subscriber's data can be transmitted to the speed matching and multiplexing / demultiplexing controller 6 to produce data in the same form as that of the asynchronous terminal accommodated in the public telephone network.

4 is a flowchart of the packet assembling and disassembly processing procedure by the control unit 9, where (A) is assembly related and (B) is disassembly related.

First, the processing procedure related to the assembly initializes the present invention (20), and maintains the control unit 9 in the standby state after the initialization (30).

It is examined 40 whether there is an interrupt request from the HDLC matcher 7 indicating that it has received pure packetization information from the speed match and multiplex / demultiplex controller 6.

If there is no interrupt request as a result of the above investigation, the process returns to the standby state 30, and if there is any interruption request, the packetized information is completely packetized by adding a header having various information to the purely packetized information (50), and the packetized information is transferred to the common memory (9). Store (60).

The packet bus matching unit 10 transmits the complete packetization information stored in the common memory 9 to the packet processing device 3 through the packet bus device so as to receive packet service (70).

After receiving the packet service, the controller 9 checks whether there is an interrupt request HDLC matching unit 7 (80). If the interruption result is from the HDLC matching unit 7, the process returns to step 50. If there is no interrupt request, the process returns to step 30 and repeats.

Next, referring to the processing procedure related to decomposition, the present invention is initialized (90), and after the initialization, the control unit 9 is kept in the standby state (100). The control unit 9 checks whether there is an interrupt request from the packet bus matching unit 10 (110).

If there is no interrupt request as a result of the investigation, the process returns to step 100. If there is an interrupt request, the packet is removed from the past packetized information to generate pure packetized information (120).

The generated pure packetization information is stored in the common memory 8 (130). The HDLC matching unit 7 designated by the control unit 9 notifies that there is information to be transmitted to the speed and multiplex / demultiplexing controller 6 among the information stored in the common memory 8 (140).

In addition, if there is an interrupt request from the packet bus matching unit 10, the process returns to the process 120. If there is no interrupt request, the process returns to the process 100 and repeats. do.

Looking at the detailed configuration of the present invention that operates as described above, the control unit 9 is implemented by Motorola's MC68000 series of processors and a control program mounted to completely packetize a header including various information.

The common memory 8 is configured as static random access memory (SRAM) to function as a memory storage.

The packet bus matching unit 10 is implemented as two packet bus matching units 10a to 10b made of Intel's 82586 (LAN Chip), and is operated redundantly to improve data transmission reliability.

The HDLC matching unit 7 is composed of at least one HDLC matching unit 7a to 7n constituted by SGS Thomson's MK5025 (X.25) IC.

Therefore, the present invention configured and operated as described above can provide an efficient and economical packet service to the asynchronous terminal subscribers of the public telephone network when the public telephone network and the integrated information communication network are interlocked. When interlocking, there is an effect that can provide a corresponding technology.

Claims (2)

Applied to the packet assembling / decomposing apparatus 4 of the packet switching apparatus equipped with the packet call control apparatus 1, the packet bus apparatus 2, the packet processing apparatus 3, and the packet assembling / decomposing apparatus 4 In the packet assembly / decomposition controller, the speed matching and multiplex / demultiplexing controller 6 receives subscriber information, converts the header including various information into fully packetized information, and interfaces with it. The packet information is transmitted to the packet bus device 2 by the HDLC matching means 7 interfaced to the speed matching and multiplexing / demultiplexing controller 6, and the complete packetized information to the packet bus device 2, and inputted from the packet bus device 2; Complete packet information and pure interface connected to the packet bus matching means 10, the HDLC matching means 7, and the packet bus matching means 2 for interfacing the received packet information into the pure packet information. Packet The common memory 8 for storing the data, the HDLC matching means 7, the packet bus matching means 2, and the packet information connected to the common memory 8 are completely packetized and purely packetized. And a control means (9) consisting of a microprocessor and a control program for controlling. 2. A packet assembly / decomposition controller according to claim 1, wherein said packet bus matching means (2) is configured in redundancy in order to increase transmission reliability.