KR910000376B1 - Commonline signaling system in exchange - Google Patents

Abstract

The apparatus includes message processors (50a-50m) for processing the signal message so that the message is transmitted to a user or terminal, a network (51) for exchanging messages between message processors and terminal group (52a-52n), a terminal group (52a-52n) for linking signals, and a signal linker (53) for multiplexing signal data from the terminal group and transmitting via a time switch unit (41).

Description

Common line signaling device of electronic exchange

Figure 1 is a hierarchical diagram of the No.7 Common Line signaling protocol of the International Telegraph and Telephone Advisory Committee (CCITT).

2 is a block diagram of a common line signaling device of an EWSD exchange between SIEMENS, Germany.

3 is a configuration diagram of a common line signaling device of No. 5 ESS exchange of AT & T Corporation of USA.

4 is an overall configuration diagram of a common line signal device of the present invention.

5 is a schematic diagram of a common line signal device of the present invention.

6 is a schematic diagram of a group of signal terminals of the present invention.

* Explanation of symbols for main parts of the drawings

40: trunk unit 41: time switch unit

42: common line signal value 44: data link unit

43: interprocessor communication network 45: trunk unit processor

46: switch unit processor 47: link unit processor

48: access switching module processor 50a to 50n: message processing processor

51: signal terminal network 52a to 52n: signal terminal group

53: signal link interface 60: signal terminal bus interface circuit

62: signal terminal master 63: signal terminal bus

The present invention relates to a No.7 common line signaling device that provides a signal required for a call connection procedure in an electronic exchange. Particularly, the present invention is more modular in function than conventional signaling devices, improves reliability of the system, and improves maintenance and efficiency. A common line signaling device for an electronic exchange. Considering that the rapid development of data transmission and digital exchange technology has led to the demand for larger and more intelligent exchanges and various services for comprehensive information communication in the future, the role and function of the signaling device in the exchange is very important. In the inter-station signaling method of the electronic exchange, R2MFC (R2-Mulit-Frequency Compelled), which is a channel-associated signaling method in which signals are exchanged through each relay line, and one common channel that manages multiple relay lines. There is a No.7 common line signaling system that transmits switching period signal information through a line channel. The No.7 common line signaling method is capable of reducing post dialing delay (PDD), providing abundant signal capacity, improving signal system reliability, providing various services, and managing a network more efficiently than conventional R2 signaling. It is indispensable to accept the future integrated information network, and the No.7 common line signaling method uses signal messages in the form of computer communication protocol to separate the signal messages for thousands of call lines by a single channel. It is designed to be used for 64Kbps digital communication network, and it is designed to operate efficiently in the low speed operation and analog communication network below.

As shown in FIG. 1, the common line signaling device refers to a hardware device that realizes a message transfer unit in a hierarchical structure of No.7 common line signaling, and the level 4 user part is excluded from the present invention since most of it is realized by software. .

In FIG. 1, the message transfer unit is a kind of transmission protocol that reliably transmits a signal message between user part functions between two electronic exchanges, and has a hierarchical structure of levels 1,2 and 3, wherein the level 1 function is a signal data link function. The level 2 function is called a signal link function, and the level 3 function is called a symbol network function, and the dual level 3 function is roughly divided into a signal message processing function and a signal network management function.

In general, the structure of the No.7 common line signaling device takes the appropriate form according to the inherent structure of the exchange, but is largely divided into two types.

The first is realized in the form of addition of common line signaling device without fundamental modification of the exchange system structure, such as AXE-10 and EWSD exchange of Siemens, Germany. As a result, interworking with the existing system becomes complicated and the software becomes complicated.

Secondly, it can be seen in the exchange which is relatively developed later, and takes the form of realizing most functions of the common line signaling device in the powerful switching module. The representative exchange is No.5 ESS, but this No.5 ESS is also in the early stage of development. The common line signaling device is not constructed from the common line signaling device, but the common switching device is configured by modifying a part of hardware and a part of software in a packet switching device that has been developed.

Here, look at the configuration and features of the common line signaling device in a typical exchange that has been developed and operated as follows.

FIG. 2 shows the structure of the common line signaling device of the EWSD exchange of Siemens Germany. The EWSD adds the common line signaling device to the existing switching system to realize the level 1,2 and 3 functions of the message transfer unit. The level 2 function is performed in the signal terminal circuit, and the level 3 function is performed in the common line processor.

The multiplexer having the dualization structure of FIG. 2 performs the level 1 function and is connected to the trunk circuit through a switch network with 8 Mbps hardware, and the level 2 function is performed in the signal terminal circuit and one signal terminal circuit. Up to 256 signal links are accommodated in the common line signaling device of the EWSD exchange by accommodating the signal links. Here, the signal terminal control circuit controls eight signal terminal circuits. The main function is to organize the signal messages of the eight signal terminal circuits to communicate with the common network processor, and the level 3 function is performed by the common network processor. The processor has a multiprocessor structure, and includes a communication processor 1, a communication processor 2, and a main processor. The communication processor 1 is responsible for communication with four signal terminal control circuits, and the communication processor 2 is responsible for communication with a user unit. The main processor is responsible for message distribution, message routing and signaling network management.

Although this structure is well matched with the hierarchical structure of the message transfer unit protocol itself, there is a problem in that it takes a lot of time for signal information processing by increasing the number of processors that the signal message passes to the user unit.

FIG. 3 shows the structure of the common line signaling device of No. 5 ESS exchange of AT & T in the US. In FIG. 3, the level 1 path is a time switch of the signal data link inputted to the trunk unit of the trunk switching module. Is transmitted to the communication module (composed of space location and message switch) and then applied to the packet processor through the data fan fanout in the packet exchange unit of the CCITT 7 switching module through a fixed timeslot. After processing part of Level 2 function and Level 3 function for the input signal message, it performs attestation message processing function to send the message to the user part. The packet switched switching unit has several packet processors and N + K redundancy. It is operated in the form of (Redundancy).

The packet processor shown in FIG. 3 is designed to handle level 2 of the D-channel protocol or common channel signaling or internal protocol for message exchange by implementing appropriate software according to the purpose. The case consists of a packet processor for No.7 protocol processing that handles message processing functions of level 2 and level 3 of the message transfer unit, and a packet processor for communication that processes an internal protocol for communication with the trunk module to which the user belongs.

The communication packet processor handles an internal protocol for performing communication with a corresponding module and also selects a signal link to be transmitted to another station by using an outgoing routine table. Each packet switching unit of the CCITT 7 switching module Packet processors are connected by packet fanouts with a transmission rate of 10Mbps.

As described above, the packet processors of the packet switching unit perform signal message processing functions, which are sub-levels of the level 2 and level 3 functions of the No.7 protocol, while the main processor of the CCITT 7 switching module is a signal network management function and various software. It performs the interface function and the user part function is distributed to each trunk switching module and interacts with the packet processor.

Since the structure of the No.5 ESS is not a structure for realizing the inherent function of No.7 but a form realized by modifying it from the subscriber packet processing apparatus, the signal system is constructed in accordance with the hierarchical structure of the No.7 protocol. Since the switch network connection circuit, such as a speed matcher, is in a packet processor and an incoming routing process must be performed in the packet processor, each packet processor must own a large routing table.

As described above, the common line signaling device realized in the conventional electronic exchange has an appropriate type according to the unique structure of the exchange, but their common feature is that they have a hierarchical structure to meet the characteristics of the No.7 protocol.

In other words, the level 1 function is connected to the switch network by an interface circuit having a kind of multiplexer function to interact with the signal data link accommodated in the trunk circuit. The level 2 function generally has a single processor structure. It accepts and processes the signal link, and the lower level of the message processing function, which is the lower level, has a dedicated processor for distributed processing, and the higher level signal network management function concentrates on the main processor.

In addition to these common issues, the most important factors affecting the performance and efficiency of the common line signaling device of each exchange are communication method and interface structure between the level 2 processor and the level 3 processor.

In the case of the above-mentioned EWSD exchange, there are many intermediate steps via communication between the level 2 and level 3 processors, so that the reconfiguration of the signal network becomes complicated when there is an abnormality of the signal terminal or a failure of the signal link. In the case of the packet processor, in addition to the level 2 function, the lower level function of the level 3 function performs the message processing function. Therefore, each packet processor must have a large amount of routing tables. Therefore, the structure and control procedures of the packet processor are complicated. .

The present invention has the object of developing a more efficient common line signal device by improving the problems and disadvantages according to the configuration of the common line signal device as described above, the common line signal device of the present invention is the Hardware and software were removed to suit the level, and the level function of each protocol was divided and configured appropriately.

In addition, in the common line signaling apparatus of the present invention, two-step bus arbitration method of signaling terminal network and signaling terminal bus is used for communication between signal terminal and message processing processor, thereby coping with reconstruction of signal network in case of abnormal situation. In particular, since the signal terminal group has a modular structure, the present invention will be described in detail below with reference to the accompanying drawings as a common line signal device capable of maximizing efficiency by easy maintenance, operation, and management of a system.

4 illustrates a structure in which the common line signaling device of the present invention is accommodated in an access switching module of an exchange. Referring to the flow of the signal message, the signal message inputted from the signal link of the trunk circuit is a trunk unit 40 and a time unit. And connected to the common line signaling device 42 via 41 to process level 2 and level 3 functions, and then through the data link unit 44 via the interprocessor communication network 43 and the link unit processor 47. The common line signaling device, which is transmitted to the access switching module having a user part, is also transmitted to another exchange through the data link unit 44 and then through the link unit processor 47 and the interprocessor communication network 43. Is applied to (42). In this case, the common line signaling device 42 is connected to the trunk unit 40 to which the corresponding signal data link belongs through the time switch unit 41 after the processing of the level 2 and level 3 functions. As such a message can be transmitted, the signal data link may be placed in an access switching module which exclusively receives only the access switching module or the trunk unit 40 to which the common line signaling device 42 belongs.

5 is a diagram illustrating the common line signal device 42 of the present invention in more detail. The signal device also has a hierarchical structure according to the characteristics of each level so as to conform to the protocol structure of No. 7 signaling method. The signal links output from the 32 signal terminal groups 52a to 52n are connected in 32 units in the signal link interface 53 circuit, multiplexed into 2,048 Mbps signal groups, and applied to the input terminal of the time switch. Level 1 functions the signaling message to the counterpart exchange through the desired trunk circuit.

The signal link function, which is a level 2 function, is performed at the signal terminals (61a to 61n in FIG. 6) in the signal terminal groups 52a to 52n, and the signal terminals 61a to 61n are provided in order to enhance the signal device modularity of the present invention. Or modularized into 32 units to form respective signal terminal groups 52a to 52n, each having its own maintenance function in the signal terminal groups 52a to 52n, and having the required capacity of the common line signal device 42. According to the present invention, a signal terminal is composed of a 16-bit processor, a direct memory access (DMA) link controller, and a memory to process one signal link.

On the other hand, the signal network management function, which is a higher level among the signal network functions, which are level 3 functions, is performed by the access switching module processor 48, and the signal message processing functions, which are lower functions, are respectively performed by the message processing processors 50a to 50n.

The message processing processors 50a to 50n are dedicated processors for routing a signal message input from the signal terminals 52a to 52n to the corresponding user unit or for routing a message input from the user unit to the corresponding signal terminal. It is only responsible for message handling.

Since the message processing processors 50a to 50n are designed to process the signal message traffic corresponding to 8 to 10 signal terminals 61a to 61n, 64 signal link accommodating in this signaling device is n + K. Up to eight message processing processors, including redundancy, are required. Therefore, this signaling device takes the form of a dedicated processor corresponding to each level of the message transfer protocol. Since only a message processing processor needs to have a routing table without having a large routing table, there is an advantage in that a large amount of common line signaling device that requires a large quantity can be configured relatively simply.

The message processing processors 50a to 50n are routed to a system bus based on the VEM bus, a routing processor, which is a 32-bit processor module, and two communication processors and routing for communication between the interprocessor communication network and the signal terminal network. It has a multiprocessor structure consisting of 1Mbyte memory modules that store tables.

In FIG. 5, the signal terminal network 51 accommodates a maximum of 32 nodes, and each node is a kind of serial bus connected to the signal terminal groups 52a to 52n or the message processing processors 50a to 50n. It has a transmission speed and is tripled and operated in the form of Triple Modular Redundancy (TMR). Each node on the signal terminal network 51 has a unique address and is connected to a group of signal terminals 52a to 52n or a message processing processor. And each node on the signaling terminal network 51 requests a bus occupancy request to the bus arbiter when there is a message to be transmitted. In this case, the bus arbitrator assigns bus occupancy rights to each node sequentially by a round robin method.

Once a bus is assigned to a node, the sending node loads the receiving axis node address in the message frame to send and the receiving node receives the message only when it matches its own address.

FIG. 6 shows the internal structure of the signal terminal groups 52a to 52n in FIG. 5, which is comprised of 16 signal terminals 1-n (up to 32 can be accommodated), a signal terminal network, and a signal terminal bus 63. The signal terminal bus interface circuit 60 for connection, each signal terminal 61a to 61n, the signal terminal master 62 which is in charge of maintenance of the bus, and the signal terminal bus 63 which interconnect them, and the signal The terminal bus interface circuit 60 has a function of physically connecting the signal terminal bus 63 and a node on the signal terminal network, and the reference signal required for data transmission and bus arbitration in the signal terminal bus 63. It also has the function of generating.

The signal terminal bus 63 is divided into a data transmission bus and a maintenance bus. The data transmission bus is a triplex serial bus similar to the aforementioned signal terminal network 51 or bidirectional communication once occupied by a bus. It is possible to transmit up to 4 Mbps, and the arbitration mode on the signal terminal bus 63 also uses a round robin method, and each signal terminal 61a to 61n is sequentially connected to the signal terminal network 51 by a sequential address by a unique address. Communication with the message processing processors 50a to 50n, and a maintenance bus of the signal terminal bus 63 is in charge of maintenance of a group of signal terminals and is responsible for maintenance of each signal terminal. By reporting relevant maintenance information to the higher level access switching module processor 48, the system can be maintained, operated and managed effectively. It was to group sex.

On the other hand, the signal terminal groups 52a to 52n triple the signal terminal bus 63 to operate in a TMR form in order to improve reliability, and the signal terminal bus interface circuit 60 and the signal terminal master 62 consider the importance thereof. 16 or 32 signal terminals (61a to 61n) operate in the form of redundancy of n + K (K = 30%), so that in case of failure of one signal terminal, redundant signal terminals (61a to 61n) ) To allow for rapid transfer.

As shown in FIG. 5 and FIG. 6, the signal terminals 61a to 61n performing the level 2 function and the signal message processing function among the level 3 functions are performed, and the message processing processors 50a to 50n serving as the processor are the signal terminal buses. 63) and the communication is performed via the signal terminal network 51, so that the intermediate step is much smaller than that of the EWSD switch. Also, by using the signal terminal network 51, the failure of the signal link 32 and the signal terminal ( In case of abnormalities such as the failure of 61a to 61n) and the failure of the message processing processor, the reconstruction of the signal network becomes very easy, and the maintenance and management of the system can also be achieved by taking a modular structure.

That is, the signal terminals 61a to 61n are first selected in the signal terminal bus 63, and the signal terminal group is secondly selected in the signal terminal network 51 so that communication between any signal terminal and any message processing processor This is because the two-step bus arbitration method can be performed quickly and easily.

The signal link interface 53 of FIG. 5 converts the signal data links of each signal terminal 61a to 61n into 32 units and converts them into a data sequence of 2,048 Mbps (64 Kbps x 32 = 2.048 Mbps). Connected.

In addition to the data transfer rate conversion function, this circuit generates the reference signals required by each signal terminal, allowing the signal terminal to send and receive No.7 signal messages over 64Kbps or 56Kbps signal data links. Since each component in the line signal device is composed of full redundancy and triple redundancy or redundancy of n + K, it can be operated efficiently to cope with abnormal cases.

As described above, the common line signaling device of the present invention can maximize the processing efficiency of the protocol because the hardware structure is set to suit each level of the message transfer unit protocol, and it is unnecessary to compare the hardware with the EWSD and the No. 5 ESS exchanger. The advantages of eliminating software and conventional common line signaling devices are so subtle that the division of functions of each part is ambiguous, or hardware is formed by combining various levels of functions, resulting in inefficiency of hardware and software. Although there are disadvantages, the device of the present invention can prevent the above disadvantages because the hardware is configured by appropriately dividing the function of each protocol level.

In other words, the signal data link function, which is a level 1 function of the No.7 message transfer unit protocol, is performed by the signal link interface circuit 53, and the signal link function, which is a level 2 function, is used by the signal terminals 61a to 61n, which are dedicated processors, among the level 3 functions. The signal message processing function, which is a function, is processed by the message processing processors 50a to 50n, respectively, and the signal network management function, which is a higher level function among the level 3 functions, is concentrated in the access switching module processor 48 to increase processing efficiency at each level. It was made.

In addition, in the common line signaling apparatus of the present invention, a two-step bus arbitration method is used for communication between the signal terminals 61a to 61n and the message processing processors 50a to 50n, thereby quickly coping with the reconfiguration of the signal network when an abnormal situation occurs. In particular, since the signal terminal groups 52a to 52n have a modular structure, the system is easy to maintain, operate, and manage, thereby maximizing efficiency, and also in case of increasing the capacity of the signal system. Increasing the number of signal terminals from 16 to 32 at 52a to 52n, and thus increasing the number of message processing processors 50a to 50n to suit the amount of signal message traffic, doubles the signal device capacity of the present invention. Because of this, the capacity increase problem of the system can be easily solved.

Claims (2)

A common line signaling device of an electronic switch, comprising: a plurality of message processing processors (50a) for performing a signal message processing function for routing a message input from a user to a corresponding signal terminal or a signal message input from a preferred terminal to a corresponding user part; 50n, a coral terminal network 51 which performs message exchange while interconnecting the message processing processors 50a to 50n and the signal terminal groups 52a to 52n, and a signal terminal for performing a signal link function as a level 2 function. And a signal link interface 53 for performing a level 1 function of multiplexing the groups 52a to 52n and the signal data from the signal terminal groups 52a to 52n and transferring them to the time switch unit 41. Common line signaling device for an electronic exchange. The signal terminal bus interbase according to claim 1, wherein the signal terminal groups 52a to 50n performing the level 2 function perform the connection with the signal terminal network 51 and generate a reference signal for data transmission and bus arbitration. The circuit 60, the signal terminal master 62 which performs maintenance of each signal terminal and the bus, and the signal terminal interface circuit 60 and the signal terminal network 51 are sequentially processed by a unique address. The signal terminal bus comprises a plurality of signal terminals 61a to 61n which perform a signal link function while communicating with the processors 50a to 50n, and a data transmission bus and a maintenance bus which can perform bidirectional communication using a triple serial bus. A common line signaling device for an electronic exchange consisting of signal terminal buses (63) interconnecting an interface (60), signal terminals (61a to 61n), and a signal terminal master (62).

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