KR950006428B1 - S-ram memory cell - Google Patents

S-ram memory cell Download PDF

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Publication number
KR950006428B1
KR950006428B1 KR1019920026899A KR920026899A KR950006428B1 KR 950006428 B1 KR950006428 B1 KR 950006428B1 KR 1019920026899 A KR1019920026899 A KR 1019920026899A KR 920026899 A KR920026899 A KR 920026899A KR 950006428 B1 KR950006428 B1 KR 950006428B1
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KR
South Korea
Prior art keywords
memory cell
cell
transistors
sram
resistance
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KR1019920026899A
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Korean (ko)
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KR940016271A (en
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황준
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현대전자산업주식회사
김주용
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Priority to KR1019920026899A priority Critical patent/KR950006428B1/en
Publication of KR940016271A publication Critical patent/KR940016271A/en
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Publication of KR950006428B1 publication Critical patent/KR950006428B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

The cell has high integrated rate as sharing a load resistor with adjacent cells. It shares high resistors (R1'-R4') connected to transistors (Q2,Q8,Q9,Q17,Q23) of each unit cell with transistors (Q9,Q10,Q15,Q16) of adjacent unit cell.

Description

에스램 메모리 셀SRAM memory cell

제1도는 종래의 SRAM 메모리 셀 등기 회로도.1 is a conventional SRAM memory cell registration circuit diagram.

제2도는 본 발명에 다른 SRAM 메모리 셀 등기 회로도.2 is an SRAM memory cell registration circuit diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

Q1 내지 Q24 : 트랜지스터 R1 내지 R8 : 저항Q1 to Q24: transistors R1 to R8: resistors

R1 내지 R4' : 저항R1 to R4 ': resistance

본 발명은 SRAM (Static RAM) 메모리 셀에 관한 것으로, 특히 부하 저항을 인접 셀과 공유 하게 함으로써 구집적도를 실현하는 SRAM 메모리 셀에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to SRAM (Static RAM) memory cells, and more particularly, to SRAM memory cells that realize density by sharing a load resistance with adjacent cells.

종래의 SRAM 을 제1도를 통하여 살펴보면, 도면에서 Q1 내지 Q16은 트랜지스터, R1 내지 R8은 저항을 각각 나타낸다.Looking at the conventional SRAM through FIG. 1, Q1 to Q16 represent transistors and R1 to R8 represent resistors, respectively.

제1도의 도면부호 A는 SRAM 단위 셀로서, 4개의 트랜지스터(Q1-Q4)과 2개의 고저항(R1,R2)를 형성하여 매모리 셀을 형성됨을 도시해 주고 있다.In FIG. 1, reference numeral A denotes an SRAM unit cell, in which four transistors Q 1 -Q 4 and two high resistors R 1 and R 2 are formed to form a memory cell.

그러나 상기 종래의 SRAM은 고저항 형성을 위한 패턴이 불필요하게 많아 이에따른 단위 셀의 크기 증가 및 패턴의 고밀집성, 제조공정의 포토마스크 제작, 식각공정의 어려움을 초래하는 문제점이 있었다.However, the conventional SRAM has a problem that the pattern for forming a high resistance is unnecessary, thereby increasing the size of the unit cell, high density of the pattern, photomask fabrication of the manufacturing process, difficulty in etching process.

따라서 상기 문제점을 해결하기 위하여 안출 된 본 발명은 단위 셀 형성에 있어서 고저항 패턴 형성시 종래의 상기 고저항을 인접 셀과 함께 공유하게 함으로써 단위셀의 크기를 감소시키고 고집적도를 실현 할 수 있는 SRAM 메모리 셀을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention provides a SRAM capable of reducing the size of a unit cell and realizing a high density by sharing the conventional high resistance with an adjacent cell when forming a high resistance pattern in forming a unit cell. The purpose is to provide a memory cell.

상기 목적을 달성하기 위하여 본 발명은, 인접한 단위 셀의 연속적 구성으로 이루어지는 에스램(SRAM)메모리 셀에 있어서, 각각 단위셀의 트랜지스터(Q2,Q8,Q9,Q17,Q23)에 연결되는 고저항(R1' 내지 R4')을 인접한 단위셀의 트랜지스터(Q9,Q10,Q15,Q16)과 공유하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a high-resistance (SRAM) memory cell having a continuous configuration of adjacent unit cells, each connected to transistors Q2, Q8, Q9, Q17, and Q23 of the unit cell. R1 'to R4' are shared with transistors Q9, Q10, Q15 and Q16 of adjacent unit cells.

이하, 첨부된 도면 제2도를 참조하여 본 발명에 따른 일실시예를 상세히 설명하면, 도면에서 Q1 내지 Q24는 트랜지스터, R1' 내지 R4'는 저항을 각각 나타낸다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 2. In the drawings, Q1 to Q24 represent transistors, and R1 'to R4' represent resistances, respectively.

본 발명에서는 종래와는 달리 제2도에 도시된 바와 같이 인접셀과 함께 고저항을 공유하게 형성한다.Unlike the related art, in the present invention, as shown in FIG. 2, high resistance is formed together with the adjacent cells.

그리고 고저항을 형성하는 불순물 이온 주입되지 않은 폴리실리콘막을 증착시켜 선택적으로 이온 주입을 실시하여 이온주입이 되지 않는 폴리실리콘막이 고저항을 형성하도록 한다.In addition, a polysilicon film that is not implanted with impurity ions to form a high resistance is deposited to selectively perform ion implantation so that the polysilicon film that is not ion implanted forms a high resistance.

이는 제1도의 고저항 R1 내지 R8을 제2도의 저항 R1' 내지 R4'로 인접 셀과 중복시켜 공유하도록 제작한다. 즉, 저항 R2과 R3는 R1'으로, 저항 R6와 R6은 R3'으로 형성한다.This is designed to be shared by overlapping and neighboring cells to a first degree and resistors R1 to R8 with the second-degree resistance R 1 'to R 4'. That is, resistors R2 and R3 are formed of R1 ', and resistors R6 and R6 are formed of R3'.

이경우 SRAM 작동시 특별한 데이타의 읽기/쓰기시 비트선, 반전 비트선, 반전 비트선 및 워드선에 의해서 1개의 셀이 선택되고, 모든 단위 셀이 고저항 전단에 5V인가 되나 실질적인 동작은 선택된 셀에만 작동하게되므로 종성과 같은 칩 자체의 읽기/쓰기 동작을 동일하게 수행하게 된다.In this case, one cell is selected by bit line, inverted bit line, inverted bit line and word line when reading / writing special data during SRAM operation, and all unit cells are 5V in front of high resistance, but the actual operation is performed only in the selected cell. This allows the chip to perform the same read / write operations as the slave itself.

상기와 같이 이루어지는 본 발명은 고저항의 공유로 SRAM 단위 셀의 크기를 축소 수 있어 고집적화를 실현 할 수 있을 뿐만 아니라, 이 축소된 면적을 이용하여 더욱 저항의 길이를 증가시켜 종래의 저항보다 더욱 높은 저항 값을 얻을 수 있는 효과가 있다.The present invention made as described above can reduce the size of the SRAM unit cell by sharing high resistance, thereby realizing high integration, and further increase the length of the resistance by using the reduced area, which is higher than the conventional resistance. The resistance value can be obtained.

Claims (2)

인접한 단위 셀의 연속적 구성으로 이루어지는 에스램(SRAM) 메모리 셀에 있어서, 각각의 단위셀의 트랜지스터(Q2,Q8,Q9,Q17,Q23)에 연결되는 고저항(R1' 내지 R4')을 인접한 단위셀의 트랜지스터(Q9,Q10,Q15,Q16)과 공유하는 것을 특징으로 하는 SRAM 메모리 셀.In an SRAM memory cell having a continuous configuration of adjacent unit cells, the high resistances R1 'to R4' connected to the transistors Q2, Q8, Q9, Q17, and Q23 of each unit cell are adjacent units. An SRAM memory cell characterized by sharing with cell transistors (Q9, Q10, Q15, Q16). 제1항에 있어서, 상기 인접하는 단위셀이 공유 저항은 불순물이 주입되지 않은 폴리실리콘막인 것을 특징으로 SRAM 메모리 셀.The SRAM memory cell of claim 1, wherein the adjacent unit cell is a polysilicon film in which impurities are not injected.
KR1019920026899A 1992-12-30 1992-12-30 S-ram memory cell KR950006428B1 (en)

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KR950006428B1 true KR950006428B1 (en) 1995-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7486392B2 (en) 2005-06-30 2009-02-03 Samsung Electronics Co., Ltd. Method of inspecting for defects and apparatus for performing the method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003133441A (en) * 2001-10-22 2003-05-09 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7486392B2 (en) 2005-06-30 2009-02-03 Samsung Electronics Co., Ltd. Method of inspecting for defects and apparatus for performing the method

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