KR950005560B1 - Timer system - Google Patents

Abstract

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Description

Timer system

1 is a diagram illustrating a first timer according to the present invention.

2 is a view for explaining a second timer according to the present invention.

* Explanation of symbols for main parts of the drawings

2: timer 9: timer bus system

The present invention relates to a timer system for use in control applications such as vehicle engine control, robotics, embedded control applications, anti-lock braking systems (ABS), and the like.

Generally, a timer system used for vehicle engine control purposes includes a processing unit (hereinafter referred to as an execution unit) for processing operation information obtained from a specific part of a vehicle engine, such as a flywheel, for example. The execution unit is coupled to a microprocessor whose function is to control the operation of the engine. Many parameters for monitoring this are monitored and controlled. Therefore, in a timer system generally there are a number of execution units, each of which processes information obtained from different parts of the engine.

The timer system also includes a clock timer coupled to each of the execution units. The execution unit uses a clocked signal, which is a sawtooth signal in the form of a progressive counting binary word that counters up from zero in a modular fashion to process information. The microprocessor makes it possible to control engine operation such as, for example, an ignition system, a fuel system, in response to the data provided by the execution unit.

Known timer systems have one clock timer and one set of execution units for information processing. The processing power of the execution unit is limited to the function of using one clock signal and in order to control the operation of the engine, the microprocessor must execute a plurality of operations, which increases the cycle time for motoring each of the parameters. The resolution of the monitoring process is poor because the microprocessor needs more time to motor each parameter and the parameters have to be updated in short time intervals. This reduces the accuracy of the control system.

For example, for controlling the fuel injection system of a vehicle, it is important that the fuel injection device valve opens at the exact time of the engine cycle and closes after a certain time. To do this, the microprocessor first compares the signal provided by the engine's detector with engine data in the form of a lookup table to determine the engine's speed and position. When the engine reaches some speed and position, the microprocessor generates a signal to open the valve. The microprocessor then clicks on the opening of the valve so that the valve opens for only a predetermined period of time. As such, in order to control the fuel injector system, a significant amount of microprocessor processing time is required.

It is therefore an object of the present invention to provide an improved timer system.

A timer system provided in accordance with the first aspect of the invention comprises a plurality of processing means, a plurality of counting means, and a bus means for coupling the plurality of counting means to the plurality of processing means, wherein the plurality of processing Means each receive a signal from said plurality of counting means, and while one of said plurality of processing means receives a signal from a first counting means of said plurality of counting means, The bus means is arranged such that at least one processing means of the plurality of processing means, which may be the one processing means, receives a signal from at least a second counting means of the plurality of counting means.

In a preferred embodiment, the bus means consists of a first bus, a second bus and a third common bus. In other words, the first bus is arranged to couple at least the first counting means of the plurality of counting means to at least one of the plurality of counting means, and the second bus comprises at least the second counting means of the plurality of counting means. And arranged to be coupled to at least one other of the plurality of processing means, and the third common bus is arranged to couple any of the counting means to any of the plurality of processing means.

The plurality of counting means may include a timer for providing a signal related to an external clock source, a timer for providing a real time signal, and a timer for providing a sawtooth signal counting up from zero in a modular manner.

Thus, each processing means, due to the flexibility of the bus means according to the invention, accesses two timers simultaneously or sequentially to process the provided data. Thus, much of the processing to be performed by the microprocessor is reduced, which reduces cycle time and improves the resolution of the monitoring process.

Two timers according to the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, the overall structure of a timer according to the first embodiment of the present invention is shown. The timer 2 consists of three timer counters 10a-c coupled to twelve execution units 11a-1 via a timer bus system 9.

The timer bus system 9 of the first embodiment has two 16-bit buses X1 and Y1. The buses X1 and Y1 may switch the timer counters 10a, 10b and 10c by switches 14a, 14b and 14c.

Each switch 14a-c has a pair of on / off switches under separate control of the XSEL and YSEL selection logic 15a-c and 16a-c. A microprocessor (not shown) coupled to communicate with the timer enables the selection logic 15a-c and 16a-c to determine which timer counter is connected to which bus. For example, buses X1 and Y1 both derive their respective signals from counter 10a or one bus derives signals from timer counter 10a while the other bus derives signals from timer counter 10b. To derive.

The three timer counters 10a-c are connected to two buses X1 and Y1 in the following manner.

a) Depending on the control bit polarity of the respective XSEL selection logic 15a and YSEL selection logic 16a, the timer counter 10a is connected to the bus X1 or Y1.

b) Depending on the control bit polarity of each of the XSEL selection logic 15b and YSEL selection logic 16b, the timer counter 10b is connected to bus X1 or Y1, and also to avoid contention of the bus, The logic connection is embodied in hardware using the control bits of the XSEL selection logic 15a and YSEL selection logic 16a of the timer counter 10a.

c) Depending on the control bit polarity of the respective XSEL selection logic 15c and YSEL selection logic 16c, the timer counter 10c is connected to the bus X1 or Y1, and the connection is also made to the timer counters 10a and 10b. Is specified in hardware using a selection logic control bit.

The timer counter 10a will provide a sawtooth signal in the form of a progressive binary word counting up from zero in a modular manner. Different timers provide different types of counting signals. That is, for vehicle engine control applications, timer counter 10b provides a signal related to an external clock source, such as an engine angle detector, and timer counter 10c provides a real time signal. In this manner, at any one moment, two of the timer counters 10a-c drive X1, Y1, and as a result, the execution unit 11a-1 coupled to the timer bus system 9 causes the bus X1, Y1. Use timer counter signals from For example, the execution unit 11a uses two synchronization signals from the timer counter 10a or the timer counters 10a and 10b, or the two execution units 11a and 11b are respectively timer counters 10a. Or use two synchronization signals from timer counters 10a, 10b.

Although the invention is described with reference to two bus timer bus systems, the two buses X1 and Y1 are each divided by four buses under switches (shown in dashed lines in FIG. 1) under microprocessor control. Provides X1, X2, Y1, and Y2.

The timer counters are arranged such that, for example, counters 10a and 10b drive buses X1 and Y1 while counter 10c drives buses X2 and Y2. In fact, by connecting the two buses X1 and X2 and two buses Y1 and Y2 by means of a switch, both the combined Xbus and the combined Ybus can be switched to any timer counters 10a-c. Furthermore, for a timer with n timer counters, the timer bus system can be configured with 1 to n buses, where n is a positive integer.

In FIG. 2, the second timer 102 according to the invention consists of five execution units 111a-e and three timer counters 110a-c coupled together via a timer bus system 109. . The operation principle of the timer 102 is the same as that of the timer 2 described with reference to FIG. 1, and the same parts are written with the same reference numerals plus 100. FIG.

The timer bus system 109 has three 16-bit buses X1, Y1 and XY. Bus X1 is driven by timer counters 110b and 110c, bus Y1 is driven by timer counter 110a, and common bus XY is driven by timer counters 110a-c. A microprocessor (not shown) selects which bus the timer count is to be connected to via bus interface 120. The bus interface 120 communicates with the microprocessor via the data bus 122 and with the timer counters 110a-c and execution units 111a-e via the data bus 124. The timer counters 110a-c and execution units 111a-e are each coupled to an external pin 126.

The timer system 102 may at least execute a unit 111a-e to process a signal from one or two of the timer counters 110a-c in response to information received from a microprocessor and / or each external pin. Allow one. For example, the processing performed by the execution unit 111a may store (i.e., "get" an event) the instantaneous value of the timer counter 110a in response to an external signal from a microprocessor or an external pin or the timer count value. Comparing the previously stored values with each other and generating an output signal when the values match.

Thus, in the case of a vehicle engine control application, the present invention uses a value generated by a timer counter related to an engine parameter to be monitored so that the execution unit enables processing functions such as the acquisition and comparison, respectively, This reduces the cycle time of the microprocessor that monitors the parameters.

Another advantage of the present invention is that due to the flexibility of the timer bus system, one execution unit can simultaneously receive signals from two timer counters. Thus, the microprocessor needs to address one execution unit to enable two 'events' to be acquired or compared, and the required throughput of the microprocessor is reduced and the likelihood of 'events' being lost is also reduced.

Although the timer system according to the present invention has been described above through two bus timer bus systems, the number of buses used may vary between 1 and n, where n is the number of timer counters.

In other words, in the case of the preferred embodiment described above, the buses can be multiplexed before being coupled to each execution unit to use three buses for each timer counter. Thus, each time the execution unit requires a value of one of the timer counters, the value can be picked up instantaneously by selecting one of three buses and the best resolution is obtained. However, the three buses arranged in this manner occupy too much silicon area and thus cannot be economically realized.

In other words, if a bus is used to combine three timer counters into five or twelve execution units, the value of the timer counters must be bus connected by time multiplexing so that the minimum resolution is reduced. It can be seen that using two or three buses in accordance with the present invention provides a sufficiently large resolution but does not occupy a fairly large silicon area.

Claims (6)

In a timer system comprising a plurality of processing means (11a-1), a plurality of counting means (10a-c), and a bus means, the bus means may comprise the plurality of counting means (10a-c). Means 14a-c, 15a-c, 16a-c, 120, 124 for coupling to the processing means 11a-1, whereby each of said plurality of processing means 11a-1 is said plurality of counting A signal may be received from each of the means 10a-c, the bus means being characterized in that at least one of the plurality of processing means 11a-1 is the first counting means of the plurality of counting means 10a-c. And at the same time receiving a signal from the at least one of the plurality of processing means 11a-1 is arranged to receive a signal from at least a second counting means of the plurality of counting means 10a-c. Timer system. 2. The timer system according to claim 1, wherein said one processing means for receiving a signal from said first counting means and said one processing means for receiving a signal from said second counting means are identical processing means. 2. The apparatus according to claim 1, wherein each processing means stores an instantaneous value of the received signal in response to an external signal, or compares the received signal with a pre-memory value and outputs an output signal when the result matches. A timer system, arranged to generate. 2. The timing system of claim 1, wherein the counting means is m and the bus means comprises n buses, where n is less than or equal to m and m and n are positive integers. 5. The timer system as claimed in claim 4, wherein the bus means further comprises selection means (14a-c) for determining that n counting means of the counting means are coupled to the n buses. 5. A bus according to claim 4, wherein the bus means comprises a first bus (X1), a second bus (Y1) and a third common bus (XY), wherein the first bus (X1) is one of the plurality of counting means. At least the first counting means is coupled to at least one of the plurality of processing means, and the second bus Y1 connects at least the second counting means of the plurality of counting means to at least the Coupling to one processing means other than one processing means, wherein the third common bus (XY) couples any of the plurality of counting means to any of the plurality of processing means.