KR950004841A - Register device of data exchange system between supervisory control unit and register - Google Patents

Register device of data exchange system between supervisory control unit and register Download PDF

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Publication number
KR950004841A
KR950004841A KR1019930014088A KR930014088A KR950004841A KR 950004841 A KR950004841 A KR 950004841A KR 1019930014088 A KR1019930014088 A KR 1019930014088A KR 930014088 A KR930014088 A KR 930014088A KR 950004841 A KR950004841 A KR 950004841A
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KR
South Korea
Prior art keywords
register
control signal
address
control
data
Prior art date
Application number
KR1019930014088A
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Korean (ko)
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KR960003973B1 (en
Inventor
정상문
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박성규
대우통신 주식회사
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Priority to KR1019930014088A priority Critical patent/KR960003973B1/en
Publication of KR950004841A publication Critical patent/KR950004841A/en
Application granted granted Critical
Publication of KR960003973B1 publication Critical patent/KR960003973B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/18—Telephone sets specially adapted for use in ships, mines, or other places exposed to adverse environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Debugging And Monitoring (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

본 발명의 레지스터장치는 감시제어부와 복수의 레지스터간의 데이타 송수신에 있어서 최소의 제어라인과 데이타 버스만을 이용함으로서 전체시스템의 간소화를 도모하기 위한 것으로, 감시제어로부터 제어신호와 상기 데이타 버스를 통해 입력되는 어드레스에 상응하여 해당 어드레스를 활성화시키는 어드레스 지정부와, 감시 제어부로부터의 제어신호에 의거하여 복수의 레지스터에서의 데이타의 기록 및 판독을 위한 제어신호를 발생하는 제어신호 지정부와, 어드레스 지정부로부터의 어드레스 지정신호와 상기 제어신호 지정부로부터의 제어신호에 상응하여 데이타 버스를 통해 송수신되는 데이타를 기록/판독하기 위한 송신측 및 수신측 레지스터로 구성한 것이다.The register device of the present invention is intended to simplify the entire system by using only a minimum control line and a data bus for data transmission and reception between the supervisory control unit and a plurality of registers. The register device is input from the supervisory control via the control signal and the data bus. An address designation unit for activating the address in correspondence with the address, a control signal designation unit for generating control signals for writing and reading data in a plurality of registers based on control signals from the monitoring control unit, and from the address designation unit And a sending side and a receiving side register for recording / reading data transmitted / received through the data bus in correspondence with the address designation signal and the control signal from the control signal designation section.

Description

감시제어부와 레지스터간 데이타 교환시스템의 레지스터장치Register device of data exchange system between supervisory control unit and register

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 감시제어부와 레지스터간 데이타 교환시스템의 블록구성도, 제 2 도는 본 발명의 바람직한 실시예에 따른 감시제어부와 레지스터간 데이타 교환시스템의 레지스터장치에 대한 블록구성도, 제 3 도는 제 1 도에 도시된 데이타 교환시스템에서 송신측의 레지스터에 데이타를 기록하기 위한 타이밍도, 제 4 도는 제 1 도에 도시된 데이타 교환시스템에서 수신측의 레지스터에 데이타를 기록하기 위한 타이밍도.1 is a block diagram of a data exchange system between a supervisory control unit and a register; FIG. 2 is a block diagram of a register device of a data exchange system between a supervisory control unit and a register according to a preferred embodiment of the present invention; FIG. Fig. 4 is a timing diagram for writing data into a register on the transmitting side in the data exchange system shown in Fig. 4, and Fig. 4 is a timing diagram for writing data into a register on the receiving side in the data exchange system shown in Fig. 1. Figs.

Claims (1)

최소의 제어라인과 데이타 버스를 이용하여 감시제어부와 복수의 레지스터간에 데이타를 송수신하는 데이타 교환시스템의레지스터 장치에 있어서, 상기 감시제어부로 부터의 제어신호와 상기 데이타 버스를 통해 입력되는 어드레스에 상응하여해당 어드레스를 활성화시키는 어드레스 지정부와 ; 상기 감시제어부로 부터의 제어신호에 의거하여 상기 복수의 레지스터에서의 데이타의 기록 및 판독을 위한 제어신호를 발생하는 제어신호 지정부와 ; 상기 어드레스 지정부로 부터의 어드레스 지정신호와 상기 제어신호 지정부로 부터의 제어신호에 상응하여 데이타 버스를 통해 송수신되는 데이타를 기록/판독하기 위한 송신측 및 수신측 레지스터로 이루어진 감시제어부와 레지스터간 데이타 교환시스템의 레지스터 장치.A register device of a data exchange system for transmitting and receiving data between a supervisory control unit and a plurality of registers using a minimum control line and a data bus, wherein the register device of the data exchange system corresponds to a control signal from the supervisory control unit and an address input through the data bus. An address designation unit for activating the address; A control signal designation section for generating a control signal for writing and reading data in the plurality of registers based on the control signal from the monitoring control section; Data exchange between the supervisory control unit and the register consisting of a transmitting side and a receiving side register for recording / reading data transmitted / received through a data bus in correspondence with the addressing signal from the address specifying unit and the control signal from the control signal specifying unit. The register device of the system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930014088A 1993-07-24 1993-07-24 Register device for electronic switching system KR960003973B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930014088A KR960003973B1 (en) 1993-07-24 1993-07-24 Register device for electronic switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930014088A KR960003973B1 (en) 1993-07-24 1993-07-24 Register device for electronic switching system

Publications (2)

Publication Number Publication Date
KR950004841A true KR950004841A (en) 1995-02-18
KR960003973B1 KR960003973B1 (en) 1996-03-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930014088A KR960003973B1 (en) 1993-07-24 1993-07-24 Register device for electronic switching system

Country Status (1)

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KR (1) KR960003973B1 (en)

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Publication number Publication date
KR960003973B1 (en) 1996-03-25

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