KR970049596A - Dual system bus matcher - Google Patents

Dual system bus matcher Download PDF

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Publication number
KR970049596A
KR970049596A KR1019950053189A KR19950053189A KR970049596A KR 970049596 A KR970049596 A KR 970049596A KR 1019950053189 A KR1019950053189 A KR 1019950053189A KR 19950053189 A KR19950053189 A KR 19950053189A KR 970049596 A KR970049596 A KR 970049596A
Authority
KR
South Korea
Prior art keywords
bus
local
system bus
matching
control
Prior art date
Application number
KR1019950053189A
Other languages
Korean (ko)
Other versions
KR0175468B1 (en
Inventor
여환근
송광석
한차문
Original Assignee
양승택
한국전자통신연구원
이준
한국전기통신공사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 양승택, 한국전자통신연구원, 이준, 한국전기통신공사 filed Critical 양승택
Priority to KR1019950053189A priority Critical patent/KR0175468B1/en
Publication of KR970049596A publication Critical patent/KR970049596A/en
Application granted granted Critical
Publication of KR0175468B1 publication Critical patent/KR0175468B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2041—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with more than one idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space

Abstract

본 발명은 이중 시스템을 버스 구조를 지원하는 이중 시스템 버스 정합 장치에 관한 것으로, 이중화된 시스템 버스와의 접속을 위한 시스템 버스 정합수단; 상기 시스템 버스 정합수단에 연결되고 로컬 버스에 연결되어 이중화 된 시스템 버스와의 정합을 갖는 프로세서 모듈내에서 버스 선택을 위한 시스템 버스 제어수단; 상기 시스템 버스 제어수단에 로컬 버스로 연결되는 로컬 중앙제어수단; 및 상기 시스템 버스 제어수단이 로컬 중앙제어수단에 로컬 버스로 연결되는 로컬 메모리 수단을 구비하는 것을 특징으로 한다.The present invention relates to a dual system bus matching device supporting a bus structure of a dual system, comprising: system bus matching means for connecting to a redundant system bus; System bus control means for bus selection in a processor module coupled to said system bus matching means and having a matching with a redundant system bus coupled to a local bus; Local central control means connected to the system bus control means by a local bus; And local memory means connected to the system bus control means by a local bus to the local central control means.

Description

이중 시스템 버스 정합장치Dual system bus matcher

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 제어 시스템 구성도,1 is a block diagram of a control system to which the present invention is applied;

제2도는 본 시스템 버스 정합기의 블럭구성도,2 is a block diagram of the present system bus matcher,

제3도는 버스 송신부의 세부 블럭구성도.3 is a detailed block diagram of a bus transmitter.

Claims (4)

이중화된 시스템 버스와의 접속을 위한 시스템 버스 정합수단(2); 상기 시스템 버스 정합수단(2)에 연결되고 로컬 버스에 연결되어 이중화 된 시스템 버스와의 정합을 갖는 프로세서 모듈내에서 버스 선택을 위한 시스템 버스 제어수단(3); 상기 시스템 버스 제어수단(3)에 로컬 버스로 연결되는 로컬 중앙제어수단(4); 및 상기 시스템 버스 제어수단(3)가 로컬 중앙제어수단(4)에 로컬 버스로 연결되는 로컬 메모리 수단(5)을 구비하는 것을 특징으로 하는 이중 시스템 버스 정합장치.System bus matching means (2) for connection with a redundant system bus; System bus control means (3) for bus selection in a processor module connected to said system bus matching means (2) and having a matching with a redundant system bus coupled to a local bus; Local central control means (4) connected to the system bus control means (3) by a local bus; And local memory means (5) in which said system bus control means (3) are connected to a local central control means (4) by a local bus. 제1항에 있어서, 상기 시스템 버스 정합수단(2)은, 상기 로컬버스로부터 시스템 버스로 전달되는 경우와 시스템 버스로부터 내부 로컬버스로의 트랜잭션이 발생하는 경우 각 트랜잭션의 구별을 위한 상태감시 및 정합제어부(11); 상기 로컬 버스/시스템 버스에 연결되고 상기 상태 감시 및 정합제어부(11)에 연결되어 버스와의 데이타 송수신을 수행하는 버스송/수신부(9,10)를 구비하는 것을 특징으로 하는 이중 시스템 버스 정합장치.2. The system bus matching unit (2) according to claim 1, wherein the system bus matching unit (2) is configured to monitor and match each transaction when the transaction is transferred from the local bus to the system bus and when a transaction occurs from the system bus to the internal local bus. Control unit 11; Dual system bus matching device, characterized in that it is connected to the local bus / system bus and connected to the state monitoring and matching control unit 11 to perform data transmission and reception with the bus (9, 10) . 제2항에 있어서, 상기 버스 송신부(9)는, 상기 시스템 버스와 로컬 제어 버스에 연결되는 제어신호송신부(14); 상기 제어신호송신부(14)와 시스템 버스와 로컬 데이타 버스에 연결되는 데이터 버스 송신부(12); 상기 제어신호송신부(14)와 시스템 버스와 로컬 어드레스 버스에 연결되는 어드레스 버스 송신블럭(13)을 구비하고 있는 것을 특징으로 하는 이중 시스템 버스 정합장치.3. The system of claim 2, wherein the bus transmitter (9) comprises: a control signal transmitter (14) connected to the system bus and a local control bus; A data bus transmitter 12 connected to the control signal transmitter 14 and a system bus and a local data bus; And a control bus transmitter (14) and an address bus transmission block (13) connected to a system bus and a local address bus. 제2항에 있어서, 상기 버스 수신부(10)는, 상기 시스템 버스에 연결되고 상기 로컬 제어버스에 연결되는 제어신호수신부(17); 상기 제어신호수신부(17)와 시스템 버스 및 로컬 데이타 버스에 연결되는 데이터 버스 수신기(15); 상기 제어신호수신부(17)와 시스템 버스 및 로컬 어드레스 버스에 연결되는 어드레스 버스 수신부(16)를 구비하는 것을 특징으로 하는 이중 시스템 버스 정합장치.3. The bus receiver of claim 2, further comprising: a control signal receiver (17) connected to the system bus and connected to the local control bus; A data bus receiver 15 connected to the control signal receiver 17 and a system bus and a local data bus; And a control bus receiver (17) and an address bus receiver (16) connected to a system bus and a local address bus. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950053189A 1995-12-21 1995-12-21 Dual system bus matcher KR0175468B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950053189A KR0175468B1 (en) 1995-12-21 1995-12-21 Dual system bus matcher

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950053189A KR0175468B1 (en) 1995-12-21 1995-12-21 Dual system bus matcher

Publications (2)

Publication Number Publication Date
KR970049596A true KR970049596A (en) 1997-07-29
KR0175468B1 KR0175468B1 (en) 1999-04-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100357175B1 (en) * 1997-08-29 2002-12-18 주식회사 하이닉스반도체 Digital signal processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100357175B1 (en) * 1997-08-29 2002-12-18 주식회사 하이닉스반도체 Digital signal processor

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Publication number Publication date
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