KR960011733A - Bus control unit supporting dual data transfers on a fenced protocol bus - Google Patents
Bus control unit supporting dual data transfers on a fenced protocol bus Download PDFInfo
- Publication number
- KR960011733A KR960011733A KR1019940024345A KR19940024345A KR960011733A KR 960011733 A KR960011733 A KR 960011733A KR 1019940024345 A KR1019940024345 A KR 1019940024345A KR 19940024345 A KR19940024345 A KR 19940024345A KR 960011733 A KR960011733 A KR 960011733A
- Authority
- KR
- South Korea
- Prior art keywords
- bus
- data
- processors
- processor
- memories
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
본 발명은 여러개의 프로세서 모듈과 여러개의 메모리모듈이 연결된 팬디드 프로토콜 버스(1) 상에서 데이타 전송을 할 때, 한번의 버스전송을 동시에 두 곳의 메모리로 데이타를 전송할 수 있도록 지원하는 버스 제어장치에 관한 것으로, 버스(1)로 신호를 구동하거나 받아 들이는 버스신호 수신 및 구동기(20)와, 버스(1) 상에서 구동되는 전송형태를 감시하고 또 데이타 전송을 위한 전송형태를 구동하는 버스 감시기(30)와, 자신의 위치를 가지고 데이타의 소유권을 비교하는 ID 비교기(40) 및, 이들을 제어하기 위한 버스 제어기(10)로 구성된다. 이로써, 본 발명은 프로세서에 의해 값이 변경된 캐쉬 데이타를 가진 프로세서 모듈이, 그 데이타를 요청한 다른 프로세서 모듈의 캐쉬로 데이타를 전송하면서 동시에 메모리모듈에도 해당 어드레스의 데이타를 변경시키고자 하는 경우에 유용하게 사용될 수 있다.The present invention provides a bus controller that supports data transfer to two memories at the same time when performing data transfer on the PANDED protocol bus (1) to which multiple processor modules and multiple memory modules are connected. A bus signal receiving and driver 20 for driving or accepting a signal to and from a bus 1 and a bus monitor for monitoring a transmission mode driven on the bus 1 and driving a transmission mode for data transmission ( 30), an ID comparator 40 for comparing ownership of data with its position, and a bus controller 10 for controlling them. Accordingly, the present invention is useful when a processor module having cache data whose value is changed by a processor wants to transfer data to the cache of another processor module that has requested the data, and at the same time change the data of the corresponding address in the memory module. Can be used.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명의 구성도.2 is a block diagram of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940024345A KR960012358B1 (en) | 1994-09-27 | 1994-09-27 | Bus controller for supporting double data transfer on pended protocol bus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940024345A KR960012358B1 (en) | 1994-09-27 | 1994-09-27 | Bus controller for supporting double data transfer on pended protocol bus |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960011733A true KR960011733A (en) | 1996-04-20 |
KR960012358B1 KR960012358B1 (en) | 1996-09-18 |
Family
ID=19393607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940024345A KR960012358B1 (en) | 1994-09-27 | 1994-09-27 | Bus controller for supporting double data transfer on pended protocol bus |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960012358B1 (en) |
-
1994
- 1994-09-27 KR KR1019940024345A patent/KR960012358B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960012358B1 (en) | 1996-09-18 |
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