KR960011733A - Bus control unit supporting dual data transfers on a fenced protocol bus - Google Patents

Bus control unit supporting dual data transfers on a fenced protocol bus Download PDF

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Publication number
KR960011733A
KR960011733A KR1019940024345A KR19940024345A KR960011733A KR 960011733 A KR960011733 A KR 960011733A KR 1019940024345 A KR1019940024345 A KR 1019940024345A KR 19940024345 A KR19940024345 A KR 19940024345A KR 960011733 A KR960011733 A KR 960011733A
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South Korea
Prior art keywords
bus
data
processors
processor
memories
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KR1019940024345A
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Korean (ko)
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KR960012358B1 (en
Inventor
김성운
신상석
심원세
윤석한
Original Assignee
양승택
재단법인 한국전자통신연구소
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Priority to KR1019940024345A priority Critical patent/KR960012358B1/en
Publication of KR960011733A publication Critical patent/KR960011733A/en
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Publication of KR960012358B1 publication Critical patent/KR960012358B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

본 발명은 여러개의 프로세서 모듈과 여러개의 메모리모듈이 연결된 팬디드 프로토콜 버스(1) 상에서 데이타 전송을 할 때, 한번의 버스전송을 동시에 두 곳의 메모리로 데이타를 전송할 수 있도록 지원하는 버스 제어장치에 관한 것으로, 버스(1)로 신호를 구동하거나 받아 들이는 버스신호 수신 및 구동기(20)와, 버스(1) 상에서 구동되는 전송형태를 감시하고 또 데이타 전송을 위한 전송형태를 구동하는 버스 감시기(30)와, 자신의 위치를 가지고 데이타의 소유권을 비교하는 ID 비교기(40) 및, 이들을 제어하기 위한 버스 제어기(10)로 구성된다. 이로써, 본 발명은 프로세서에 의해 값이 변경된 캐쉬 데이타를 가진 프로세서 모듈이, 그 데이타를 요청한 다른 프로세서 모듈의 캐쉬로 데이타를 전송하면서 동시에 메모리모듈에도 해당 어드레스의 데이타를 변경시키고자 하는 경우에 유용하게 사용될 수 있다.The present invention provides a bus controller that supports data transfer to two memories at the same time when performing data transfer on the PANDED protocol bus (1) to which multiple processor modules and multiple memory modules are connected. A bus signal receiving and driver 20 for driving or accepting a signal to and from a bus 1 and a bus monitor for monitoring a transmission mode driven on the bus 1 and driving a transmission mode for data transmission ( 30), an ID comparator 40 for comparing ownership of data with its position, and a bus controller 10 for controlling them. Accordingly, the present invention is useful when a processor module having cache data whose value is changed by a processor wants to transfer data to the cache of another processor module that has requested the data, and at the same time change the data of the corresponding address in the memory module. Can be used.

Description

펜디드 프로토콜 버스 상에서 이중 데이타 전송을 지원하는 버스 제어 장치Bus Control Unit Supporting Dual Data Transfers over the Fended Protocol Bus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 구성도.2 is a block diagram of the present invention.

Claims (1)

펜디드 프로토콜 버스(1)에 각각 연결되는 적어도 두개 이상씩의 프로세서들 및 메모리들을 포함하는 다중 프로세서 시스템에서 상기 프로세서들 중 어느 하나에 의해 요청된 데이타가 상기 메모리들 중 어느 하나로부터 상기 버스(1)를 통해 읽혀지게 하고 그리고 상기 프로세서들 중 어느 하나에 의해 쓰여지는 데이타가 상기 버스(1)를 통해 상기 메모리들 중 어느 하나로 보내지게 하는 버스 제어 수단에 있어서; 상기 버스 제어 수단은 상기 프로세서들 각각과 상기 버스(1) 사이에 연결되는 적어도 두개 이상의 버스 제어 모듈들을 포함하고; 상기버스 제어 모듈들 각각은 자신이 연결된 프로세서가 상기 메모리들 중 어느 하나 및 다른 프로세서들 중 하나로 데이타를 동시에 전송하는 이중 데이타 전송을 위한 소정의 제어 동작을 수행하는 제1수단(10)과, 상기 제1수단(10)에 의해 제어되어서 상기 버스(1) 상에 구동된 신호들을 받아들이거나 상기 버스(1)로 신호들을 구동하는 제2수단(20)와, 상기 프로세서들 중 어느 하나가 구동하는 사이클의 형태에 따라 상기 버스(1)의 버스 전송을 위한 전송 형태를 생성하고 그리고 상기 버스(1)에서 구동되는 전송 형태를 보고 그 전송에 참가해야 할지를 결정하여 상기 제1수단(10)으로 알려주는 제3수단(30)과, 상기 프로세서들 중 어느 하나가 보내는 데이타를 받아야 하는 상기 프로세서들 중 다른 하나 및 상기 메모리들 중 다른 하나를 나타내는 데스티네이션 아이덴티피케이션(DI) 신호를 받아들여서 자신이 연결된 프로세서의 상기 버스(1) 상에서의 위치를 나타내는 지오그래픽 어드레스(GA) 신호와 비교하여 전송된 데이타가 자신이 원하는 것인지를 알아내고, 이에 따라 상기 버스(1) 상에 구동되고 있는 데이타가 자신이 연결된 프로세서의 것임을 나타내는 myid 신호를 발생하여 상기 제1수단(10)으로 전달하는 제4수단(40)을 포함하는 것을 특징으로 하는 펜디드 프로토콜 버스 상에서 이중 데이타 전송을 지원하는 버스 제어 장치.In a multiprocessor system comprising at least two or more processors and memories, each connected to a pending protocol bus 1, data requested by any one of the processors is transferred from one of the memories to the bus 1. Bus control means for reading data by one of the processors and sending data written by any of the processors to one of the memories via the bus; The bus control means comprises at least two bus control modules connected between each of the processors and the bus (1); Each of the bus control modules may include: first means (10) for performing a predetermined control operation for dual data transmission in which a processor to which the processor is connected simultaneously transmits data to any one of the memories and one of the other processors; A second means 20 controlled by the first means 10 to receive signals driven on the bus 1 or to drive signals to the bus 1 and driven by any one of the processors. According to the form of the cycle, a transmission form for bus transmission of the bus 1 is generated, the transmission form driven on the bus 1 is determined, and it is determined whether to participate in the transmission and notified to the first means 10. Destiny represents a third means 30, the other of the processors and the other of the memories, which one of the processors should receive data sent by It accepts a Sean Identification (DI) signal and compares it with a Geographic Address (GA) signal representing the position on the bus 1 of the processor to which it is connected to determine if the transmitted data is what it wants. Fender protocol bus, characterized in that it comprises a fourth means 40 for generating a myid signal indicating that the data being driven on the bus (1) is of the processor to which it is connected to the first means (10) Bus control unit supporting dual data transfer over the network. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940024345A 1994-09-27 1994-09-27 Bus controller for supporting double data transfer on pended protocol bus KR960012358B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940024345A KR960012358B1 (en) 1994-09-27 1994-09-27 Bus controller for supporting double data transfer on pended protocol bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940024345A KR960012358B1 (en) 1994-09-27 1994-09-27 Bus controller for supporting double data transfer on pended protocol bus

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KR960011733A true KR960011733A (en) 1996-04-20
KR960012358B1 KR960012358B1 (en) 1996-09-18

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