KR950003226Y1 - Image contour compensating circuit - Google Patents
Image contour compensating circuit Download PDFInfo
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- KR950003226Y1 KR950003226Y1 KR2019890009938U KR890009938U KR950003226Y1 KR 950003226 Y1 KR950003226 Y1 KR 950003226Y1 KR 2019890009938 U KR2019890009938 U KR 2019890009938U KR 890009938 U KR890009938 U KR 890009938U KR 950003226 Y1 KR950003226 Y1 KR 950003226Y1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic
- H04N5/208—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/142—Edging; Contouring
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/646—Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
- Networks Using Active Elements (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 고안의 회로도.2 is a circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
I : 영상신호 입력단 O : 영상신호 출력단I: Video signal input terminal O: Video signal output terminal
Q1-Q7 : 트랜지스터 R1-R26 : 저항Q1-Q7: Transistor R1-R26: Resistor
C1-C7 : 콘덴서 L1 : 인덕턴스C1-C7: Capacitor L1: Inductance
VR1-VR4 : 가변저항 FET : 전계효과 트랜지스터VR1-VR4: Variable resistor FET: Field effect transistor
DL : 딜레이 라인DL: Delay Line
본 고안은 영상신호처리 장치에 있어서 영상신호의 윤곽보정회로에 관한것으로 특히 지연선(Delay Iline)과 전계효과 트랜지스터(field effect transistor ; 이하 FET라함)를 이용한 윤곽 보정회로에 관한것이다.The present invention relates to a contour correction circuit of a video signal in a video signal processing apparatus, and more particularly to a contour correction circuit using a delay line and a field effect transistor (FET).
일반적으로 VTR에서 휘도신호 재생계의 복조출력 다음단과 디앰피시스회로 다음단에 샤프니스(sharpness)회로를 조절하여 재생시의 윤곽을 보상하여 화면의 선명도를 조절하게되는데 종래의 경우에는 제1도에 도시된 바와같이 제2트랜지스터 (Q2)와 제3트랜지스터(Q3)의 에미터사이에 접속된 제2가변저항 (VR2)을 조절하여 게인을 조정하고 상기 제2트랜지스터(Q2)의 컬렉터신호와 상기 제3트랜지스터(Q3)의 베이스신호가 컬렉터에서 반전된 기준신호와의 합에 의한 윤곽 보정을 행하고 제1가변저항(VR1)을 조절하여 윤곽량을 보정하였다.In general, in the VTR, the sharpness circuit is compensated for by adjusting the sharpness circuit after the demodulation output of the luminance signal reproducing system and the stage after the de-emphasis circuit to adjust the sharpness of the screen. As described above, the gain is adjusted by adjusting the second variable resistor VR2 connected between the emitter of the second transistor Q2 and the third transistor Q3, and the collector signal of the second transistor Q2 and the third signal are adjusted. The contour correction is performed by the sum of the base signal of the transistor Q3 and the reference signal inverted by the collector, and the contour variable is corrected by adjusting the first variable resistor VR1.
그러나 상기한 종래의 방법은 제3트랜지스터(Q3)의 콜렉터 전류(Ic)변화에따른 변동량의 변화가 심하여 화면에 줄무늬가 생기는 스트리킹(Streaking)현상이 발생할 뿐만 아니라 윤곽부분의 보상량이 불안정한 단점이 있었다.However, the conventional method described above has a drawback of streaking, which causes streaks on the screen due to a change in the amount of fluctuation caused by the change in the collector current Ic of the third transistor Q3, as well as an unstable compensation amount of the contour portion. .
따라서 본 발명의 목적은 딜레이 라인과 FET를 이용하여 고신뢰도를 갖는 영상 윤곽 보상회로를 제공함에 있다.Accordingly, an object of the present invention is to provide an image contour compensation circuit having high reliability using a delay line and a FET.
이하 본 고안을 첨부한 도면을 참조하여 설명한다.Hereinafter, with reference to the accompanying drawings of the present invention.
제2도는 본 고안의 회로도로써, 입력임피던스 매칭용저항(R1) 및 콘덴서(C1)를 통하여 베이스로 영상신호를 입력하는 제5트랜지스터(Q5)와, 상기 제5트랜지스터(Q5)의 베이스와 전원공급단자(Vcc)사이에 접속된 바이어스용 저항(R2)과, 상기 제5트랜지스터(Q5)의 베이스와 접지단자 사이에 접속된 바이어스용 저항(R3)과, 전원공급단자(Vcc)와 상기 제5트랜지스터(Q5)의 에미터 사이에 접속된 저항(R4)과, 상기 제5트랜지스터(Q5)의 에미터에 접속된 저항(R5)과, 상기저항(R5)에 접속된 콘덴서(C2)와, 상기 제5트랜지스터(Q5)의 콜렉터에 접속된 딜레이라인(DL)과, 콜렉터가 상기 딜레이라인(DL)에 접속되며 에미터가 저항(R8)을 통해 전원공급단자(Vcc)에 접속된 제6트랜지스터(Q6)와, 상기 제6트랜지스터(Q6)의 베이스에 병렬접속된 바이어스용 저항(R9, R10)과, 드레인이 상기 콘덴서(C2)에 접속되며 소오스가 상기 제6트랜지스터(Q6)의 에미터에 접속된 전계효과 트랜지스터(FET)와, 상기 전계효과 트랜지스터(FET)의 게이트에 접속된 저항(R6)과, 상기 저항(R6)에 접속된 가변저항(VR3)과, 상기 제6트랜지스터(Q6)의 콜렉터와 접지단자사이에 직렬접속된 가변저항(VR4) 및 인덕턴스(L1)와, 베이스가 저항(R11)을 통해 상기 제6트랜지스터(Q6)의 콜렉터에 접속되며 에미터가 출력단자에 접속된 제7트랜지스터(Q7)와, 상기 제7트랜지스터(Q7)의 콜렉터에 접속된 저항(R12)과, 상기 제7트랜지스터(Q7)의 콜렉터에 접속된 저항(R13)으로 구성된다.2 is a circuit diagram of the present invention, and includes a fifth transistor Q5 for inputting an image signal to a base through an input impedance matching resistor R1 and a capacitor C1, and a base and a power supply of the fifth transistor Q5. A bias resistor R2 connected between a supply terminal Vcc, a bias resistor R3 connected between a base and a ground terminal of the fifth transistor Q5, a power supply terminal Vcc and the first resistor; A resistor R4 connected between the emitters of the fifth transistor Q5, a resistor R5 connected to the emitter of the fifth transistor Q5, a capacitor C2 connected to the resistor R5, And a delay line DL connected to the collector of the fifth transistor Q5, a collector connected to the delay line DL, and an emitter connected to a power supply terminal Vcc through a resistor R8. The sixth transistor Q6, the bias resistors R9 and R10 connected in parallel to the base of the sixth transistor Q6, and the drain are connected to the cone. A field effect transistor (FET) connected to the source (C2) and a source connected to the emitter of the sixth transistor (Q6), a resistor (R6) connected to a gate of the field effect transistor (FET), and the resistance; Variable resistor VR3 connected to R6, variable resistor VR4 and inductance L1 connected in series between the collector and ground terminal of the sixth transistor Q6, and the base via resistor R11. A seventh transistor Q7 connected to the collector of the sixth transistor Q6 and an emitter connected to an output terminal, a resistor R12 connected to the collector of the seventh transistor Q7, and the seventh transistor; It consists of the resistor R13 connected to the collector of Q7.
상술한 구성에 의거 본 고안을 상세히 설명한다.Based on the above-described configuration will be described the present invention in detail.
영상입력 신호가 저항(R1) 및 콘덴서(C1)를 통과한 후 제5트랜지스터(Q5)의 베이스로 입력되면 하나의 신호는 상기 제5트랜지스터(Q5)의 콜렉터에서 위상반전되어 딜레이 라인(DL)으로 입력되고 다른 하나는 상기 제5트랜지스터(Q5)의 에미터에서 동위상 신호가 저항(R5)과 콘덴서(C2)를 통과한후 전계효과 트랜지스터(FET)의 드레인(D)으로 입력된다.When the image input signal passes through the resistor R1 and the capacitor C1 and is input to the base of the fifth transistor Q5, one signal is phase-inverted by the collector of the fifth transistor Q5 to delay the delay line DL. On the other hand, the in-phase signal from the emitter of the fifth transistor Q5 passes through the resistor R5 and the capacitor C2 and is input to the drain D of the field effect transistor FET.
이때 상기 전계효과 트랜지스터(FET)의 게이트(G) 전압은 저항(R6)과 제3가변저항(VR3)에 의해 상기 드레인(D)과 소오스(S)간의 레벨을 조절하여 제6트랜지스터(Q6)의 에미터로 입력된다.In this case, the gate G voltage of the field effect transistor FET is controlled by the resistor R6 and the third variable resistor VR3 to control the level between the drain D and the source S, thereby adjusting the level of the sixth transistor Q6. It is entered as an emitter of.
또한 상기 딜레이 라인(DL)에 반전입력된 영상신호는 소정지연되어 제6트랜지스터(Q6)의 콜렉터로 입력된다. 이때 상기 제6트랜지스터(Q6)의 콜렉터에서는 상기 지연된 반전 영상신호와 상기 에미터로 부터 인가되는 비반전 영상신호가 지연차를 가지고 윤곽부분이 살아나게 되며 제4가변저항(VR4)과 인덕턴스(L1)에 의한 직렬 피이킹에 의하여 윤곽 보정량이 조절된다.In addition, the image signal inverted and input to the delay line DL is delayed and input to the collector of the sixth transistor Q6. At this time, in the collector of the sixth transistor Q6, the delayed inverted video signal and the non-inverted video signal applied from the emitter have a delay difference, and the contour part is survived, and the fourth variable resistor VR4 and the inductance L1 are used. The amount of contour correction is adjusted by series peaking by).
상기 보정량 조절된 신호는 입력 임피던스 매칭용 저항(R11)을 거쳐 버퍼용 제7트랜지스터(Q7)의 에미터로 인가되어 출력단자(O)를 통해 영상 윤곽 보정된 신호가 출력된다.The correction amount adjusted signal is applied to the emitter of the seventh transistor Q7 for buffer through the input impedance matching resistor R11, and the image contour corrected signal is output through the output terminal O.
상술한 바와같이 영상윤곽을 보정하므로써 스트리킹이 발생되지 않고 선명한 고화질화상을 얻을 수 있는 이 점이 있다.As described above, there is an advantage that a clear high definition image can be obtained without streaking by correcting the image outline.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019890009938U KR950003226Y1 (en) | 1989-07-07 | 1989-07-07 | Image contour compensating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019890009938U KR950003226Y1 (en) | 1989-07-07 | 1989-07-07 | Image contour compensating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910003609U KR910003609U (en) | 1991-02-27 |
| KR950003226Y1 true KR950003226Y1 (en) | 1995-04-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019890009938U KR950003226Y1 (en) | 1989-07-07 | 1989-07-07 | Image contour compensating circuit |
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| Country | Link |
|---|---|
| KR (1) | KR950003226Y1 (en) |
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1989
- 1989-07-07 KR KR2019890009938U patent/KR950003226Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR910003609U (en) | 1991-02-27 |
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