KR950002721B1 - System clock producing circuit - Google Patents

Abstract

The generator provides the clock signal to the digital audio of the compact disc player. The circuit comprises; a generator conversion unit to convert a analog audio signal to first digital signal; a second conversion unit to convert modulated digital signal from the digital audio signal; a multiplexer outputting the selective data for either the first or second conversion unit; a third conversion unit outputting parallel audio data and the channel division signal for the audio data.

Description

System clock generation circuit

1 is a general CDP encoding system diagram.

2 is a frame format diagram for an audio signal according to the present invention.

3 is a system clock generation circuit diagram according to the present invention.

4 is a detailed view of one embodiment of the locking detection unit 104 according to FIG.

5 is an operation timing diagram according to FIGS. 3 and 4;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system clock generating circuit of an optical recording / reproducing apparatus such as a recordable compact disk player (hereinafter referred to as " CDP "). In particular, the present invention provides an appropriate system clock for each part of the system during digital audio recording. The present invention relates to a system clock generation circuit capable of doing so.

One of the advantages of digital audio equipment is the perfect reproduction of the original sound. Also, when recording audio, there should be no degradation in sound quality compared to the original audio source. However, when analog copying using an analog-to-digital converter, quantization noise is generated, resulting in degradation of sound quality.

Typically, the encoding system of a recordable compact disc player is shown in FIG.

When the analog signals input to the input terminals CH1 and CH2 of the system as shown in FIG. 1 are input to the L channel and R channel signals, the first and second low pass filters 2 and 3 are about 1/2 times the sampling frequency. Pass only signals in the audible frequency range. In the first and second sample and hold circuits 5 and 6, the audio signal passing through the low pass filters 2 and 3 is generated by the crystal oscillator 10 and the timing unit 20, that is, a unit of 44.1 KHz. Take sample data with This data is quantized by the first and second analog / digital converters 8, 9. As described above, the encoding system performs error correction and modulation and demodulation by using audio data quantized by digital values by the sample and hold circuits 5 and 6 and the analog / digital converters 8 and 9. The quantized audio data is input to the error correcting unit 200 according to a predetermined clock generated by the crystal oscillator 10 and the timing unit 20 through the audio interface unit 100. The error correction unit 200 mixes the input 12-byte L-channel audio data and the 12-byte R-channel audio data according to a predetermined method, generates 4 bytes of Q parity, and then selects the total 28 bytes of data. 4 bytes of P parity are generated according to the method of mixing and then 32 bytes of total data (24 bytes of audio data + 4 bytes of Q parity + 4 bytes of P parity) are subjected to the crystal oscillator 10 and the timing unit 20. Output to the multiplexer unit 40 according to a predetermined clock generated by the. In addition, the control display encoding unit 30 generates one-byte subcode data according to a predetermined form and outputs information such as an absolute time or a relative time of a song to be recorded on the disc, and outputs it to the multiplexer unit 40. Then, the multiplexer section 40 determines the EFM (in accordance with a predetermined clock generated by the crystal oscillator 10 and the timing section 120) by subbyte data of 24 bytes, audio data of 24 bytes, and P, Q parity of 4 bytes, respectively. Eight Fourteen Modulation) output to the modulator (60). The EFM modulator 60 modulates 8-byte data into a 14-bit code according to a predetermined form, and then the control display encoder 30 for each 98 frames and sync signals generated by these codewords and the sync generator 50. Each of the 14-bit S0 and S1 subcode synchronization signals generated by the < RTI ID = 0.0 >) < / RTI > A final output (OUT) is made to the recording unit according to a predetermined force generated by the. FIG. 2 is a data format of one frame output from the encoding system as shown in FIG.

Here, the oscillator 10 and the timing unit 20 described in the description of FIG. 1 are necessary for each part of the system when an analog audio signal (R, L channel) is input to the input terminals CH1 and CH2. It can be seen that the clock is applied. When a digital audio signal processed from another CDP is input to the input terminals CH1 and CH2, the system clock cannot be provided.

That is, since the oscillator 10 and the timing unit 20 are designed to match the input of an analog audio signal, the system becomes useless when a digital audio signal is input.

Therefore, in the related art, the digital audio signal can be input to the input terminal of the system as shown in FIG. 1, but the system clock is not provided so that signal reproduction is impossible.

Accordingly, an object of the present invention is to provide a system clock generation circuit capable of generating a system clock necessary for each part of a system when recording not only analog audio but also digital audio.

According to the present invention for achieving the above object, it generates a first reference clock and a first master clock for phase synchronization with a predetermined clock signal and converts an analog audio signal applied in accordance with the clock signal to the first digital data. First conversion means for generating a second reference clock and a second master clock for phase synchronization from the applied digital audio signal, and second conversion means for demodulating and converting the digital audio signal into second digital data; A multiplexer for selectively outputting the output clock and data of the first or second converting means in response to the selection signal generated by the operation; and inputting the phase-locked reference clock from the output clock applied from the multiplexer Clock generating means for generating a locked system clock by comparing with a comparison clock of the clock; A third converting means for inputting a system clock applied from the clock generating means, a master clock applied to the multiplexing means, and serial audio data and outputting channel separation and parallel audio data for the audio data is provided in a circuit.

The parallel audio data output from the third conversion means may be applied to the data compression unit or the error correction unit together with the system clock, and the parallel audio data may be applied to the monitoring unit including the speaker together with the master clock. will be.

Hereinafter, a function according to a configuration and an operation will be described in detail with reference to the accompanying drawings.

FIG. 3 is a system clock generation circuit according to the present invention, which includes a connection diagram of the encoding system of FIG.

3 is a reference clock of a phase synchronization circuit generated in the analog / digital converter 10, the clock and data demodulator 102, and the analog / digital converter 101 and the clock and data demodulator 102, respectively. (APLLCLK, DPLLCLK), multiplexer 103 for switching audio master clocks (AMCLK, DMCLK) and serial digital audio data (ASDATA, DSDATA) by a selection signal (Sel) applied from the outside, and locking for phase synchronization Locking detection unit 104 and phase synchronizing circuit 105 for detecting a range of (LOCKING), a comparison clock (CMPCLK) and a locked system clock (SYSTEM CLK) to be a comparison signal of the phase synchronizing circuit 105 A divider circuit 106, 107, and L / R separation and 8-bit conversion circuits 108 for converting L-channel / R-channel separation and serial data into 8-bit parallel data, and the output of 108 is data. Compression section or error correction section 109 or audio recording A it is to be connected and the monitoring unit 110 to allow the. Here, the A / D converter 101 corresponds to the first conversion means, the clock and data demodulator 102 corresponds to the second conversion means, the multiplexer 103 corresponds to the multiplexing means, The phase synchronization circuit 105 and the locking detector 104 correspond to the clock generation means, and the L / R separation and 8-bit conversion circuit 108 correspond to the third conversion means.

In FIG. 3, when analog audio is input, the analog / digital converter 101 divides the internal 16.9344 (384 x 44.1 KHz) MHz to divide the reference clock APLLCLK and the audio master clock of the phase synchronization circuit. AMCLK) and converts analog audio applied according to these clocks into digital audio data, and outputs them together with the generated clocks.

In addition, when digital audio is input, the clock and data demodulator 102 outputs a reference clock APLLCLK and an audio master clock DMCLK to be used in the phase synchronization circuit 105, and demodulates the digital audio data. Output Here, the user operates the external switch to the analog input position when analog audio is provided as an input, and in the case of digital audio, to the digital input position.

Accordingly, the multiplexer 103 outputs either one of two input terminals A0, A1, A2 or * B0, * B1, * B2 according to a selection signal Sel indicating an analog / digital input, which is an external switch signal. Output through S0, S1, S2).

Here, the system clock (SYSTEM CLK) 4.321MHz must be synchronized with the master clock (MCLK) of the audio stage, which is made by the clock generator 120. This is because the frequencies of the system clock SYSTEM CLK and the master clock MCLK are different from each other but coincide with the starting point. When the locking data LOCK is generated from the locking detector 104 which detects the locking range when the reference clock PLLCLK is synchronized with the clock SYSCLK, the phase synchronization circuit 105 synchronizes with the audio master clock MCLK. A matching clock occurs. When M division and N division are performed, a comparison clock CMPCLK of a system clock system and a phase synchronization circuit can be obtained. The N division is "1" and the M division is "4". If the unlocking data is generated from the locking detection unit 104, as shown in the waveform of FIG. 5, the phase synchronization circuit 105 performs a phase delay until the locking data LOCK occurs.

The reason for this is to match the generation start point of the system clock SYSTEM CLK and the master clock MCLK.

The detailed configuration of the locking detection unit 104 is shown in FIG. 4, and FIG. 5 shows the waveform of the generation of the locking data LOCK according to FIG.

In FIG. 4, the waveform PLLCLK of FIG. 5 output from the phase synchronization circuit 105 is applied to one side input of the AND gate AND1.

In this case, the waveform appearing at the connection point A between the resistor R1 and the capacitor C1 connected to the input of the one side of the AND gate AND1 is represented by an integrated form of the waveform PLLCLK, and thus becomes waveform A of FIG. 5.

The waveform A is inverted and delayed by the inverter INV1 to become the waveform B of FIG. The reason why the waveform B appears as a square wave is that the inverter INV1 employs a Schmitt trigger type element. Accordingly, the waveform of the output line C of the AND gate AND1 becomes the waveform C of FIG. 5.

Therefore, the flop flop DF1 latches the waveform LOCK of FIG. 5 to the output terminal Q according to SYSCLK, which is the synchronization clock of FIG. 5 applied to the clock C. The waveform LOCK is the locking data (LOCK).

Accordingly, referring to FIG. 3, the audio master clock MCLK, the system clock SYSTEM CLK, and the serial digital audio data are L-channel / R-channel separation and serial data converting 8-bit paratel data. 8-bit parallel audio data is output to the data compression section or error correction unit 109 together with the system clock (SYSTEM CLK) by the 108, and 8-bit parallel audio data is monitored together with the audio master clock (MCLK). Output to the unit (110).

The system clock (SYSTEM CLK) and 8-bit parallel audio data are compressed in the case of a compact disc player that requires data compression and then lead to error correction. Input to the correction part.

The monitoring unit 10 performs a function of allowing the user to record the audio signal input at the time of recording.

In addition, phase shifting is performed for each of the analog / digital converter 101 and the clock and data demodulator 10 separately by changing the positions of the multiplexer 103 and the clock generator 120 in the configuration of FIG. It can also be switched using circuits such as multiplexers or latches.

As described above, the present invention has an advantage in that the system clock necessary for each part of the system can be properly provided even during digital audio input, thereby improving the reliability and utility of the system.

Claims (4)

1. An optical recording and reproducing apparatus, comprising: first conversion means for generating a phase synchronization first reference clock and a first master clock using a predetermined clock signal and converting an analog audio signal applied in accordance with the clock signal to first digital data; And second conversion means for generating a phase reference second reference clock and a second master clock from the applied digital audio signal, demodulating the digital audio signal, and converting the digital audio signal into second digital data. An internal comparison clock by inputting the phase synchronization reference clock from among the output clocks and data applied from the multiplexer, and a multiplexer selectively outputting the output clock and data of the first or second conversion means in response to a selection signal; Clock generating means for generating a locked system clock by comparison with the clock generating means; By entering the master clock and the serial audio data applied to the system clock and the multiplexing means being applied to the system clock generating circuit characterized by the third conversion means configured to output a channel separate and parallel audio data on the audio data. The phase synchronizing circuit according to claim 1, wherein the clock generating unit inputs a comparison clock fed back from the phase synchronizing reference clock and itself to lock and output the system clock, and the reference from the phase synchronizing circuit. And a locking detector for inputting a clock and a synchronous clock to output locking data for setting the locking of the phase synchronization circuit. The lock detection unit of claim 2, wherein the locking detection unit latches an AND gate for ANDing the reference clock and an inverse delayed clock of the reference clock, and latches an AND product output of the AND gate in response to the synchronization clock. A system clock generation circuit comprising a flip-flop to output. 4. The system clock generation circuit according to claim 3, wherein the inverted delayed clock applied to the AND gate is generated by a Schmitt trigger inverter.