KR950001895A - Method of securing contact hole overflow margin of semiconductor device - Google Patents

Method of securing contact hole overflow margin of semiconductor device Download PDF

Info

Publication number
KR950001895A
KR950001895A KR1019930010827A KR930010827A KR950001895A KR 950001895 A KR950001895 A KR 950001895A KR 1019930010827 A KR1019930010827 A KR 1019930010827A KR 930010827 A KR930010827 A KR 930010827A KR 950001895 A KR950001895 A KR 950001895A
Authority
KR
South Korea
Prior art keywords
insulating film
contact hole
mask
overlap
securing
Prior art date
Application number
KR1019930010827A
Other languages
Korean (ko)
Other versions
KR970000693B1 (en
Inventor
최양규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930010827A priority Critical patent/KR970000693B1/en
Publication of KR950001895A publication Critical patent/KR950001895A/en
Application granted granted Critical
Publication of KR970000693B1 publication Critical patent/KR970000693B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 설계(lay-out)시 최소 디자인 룰(minimum design rule)을 어길 수 밖에 없는 조밀한 지역에서 상부 도전체 콘택홀과 하부 도전체와의 오버랩여유(Overlap Margin)를 제조공정시 확보하게 하는 반도체 소자의 콘택홀 오버랩여유 확보방법에 관한 것으로, 실리콘 기판상에 소자분리 산화막을 형성한 다음 제1절연막을 형성하여 절연 및 평탄화 한 다음, 하부 도전체 라인 마스크를 사용하여 하부 도전체 라인을 형성하는 제1단계, 상기 구조 상부에 질화절연막을 형성한 다음, 오버랩 확보용 마스크를 사용하여 오버랩 확보용 마스크의 감광막패턴을 형성한 다음 상기 감광막을 이용하여 질환절연막을 식각한후, 감광막을 제거하는 제2단계, 상기 하부도전체 라인 상부에만 선택적 텅스텐을 증착하는 제3단계 및, 제3절연막을 형성하여 평탄화 한 다음, 상부 도전체 콘택홀 마스크를 이용하여 상부 도전체 콘택홀을 형성하는 제 4단계를 포함하여 이루어짐으로써, 설계시 부족한 디자인 룰을 제조공정에서 보상해 줄 수 있어, 반도체 소자의 수율 증가와 아울러 신뢰도 향상의 효과를 얻을 수 있다.The present invention provides a manufacturing process for overlap margin between an upper conductor contact hole and a lower conductor in a dense area where a minimum design rule must be violated during the layout of a semiconductor device. The present invention relates to a method for securing a contact hole overlap margin of a semiconductor device, wherein a device isolation oxide film is formed on a silicon substrate, and a first insulating film is formed, insulated and planarized, and then a lower conductive line mask is used using a lower conductor line mask. In the first step of forming a sieve line, a nitride insulating film is formed on the structure, then a photosensitive film pattern of the overlap securing mask is formed using an overlap securing mask, and then the diseased insulating film is etched using the photosensitive film. A second step of removing the photoresist film, a third step of depositing selective tungsten only on the lower conductive line, and a planarization by forming a third insulating film Next, by including the fourth step of forming the upper conductor contact hole using the upper conductor contact hole mask, it is possible to compensate for the design rule lacking in the design process in the manufacturing process, increasing the yield of the semiconductor device The effect of reliability improvement can be obtained.

Description

반도체 소자의 콘택홀 오버랩여유 확보방법Method of securing contact hole overlap margin of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 디램셀 레이아웃(lay out), 제2도(a) 내지 제2도(e)는 본 발명의 일실시예에 따른, 제1도 a-a′방향 공정 단면도, 제3도(a) 내지 제3도(d)는 본 발명의 일실시예에 따른, 제1도 b-b′ 방향 공정단면도, 제4도는 상기 제2도(d) 및 제3도(c)의 평면도이다.1 is a diagram illustrating a DRAM cell layout according to the present invention, and FIGS. 2A to 2E are cross-sectional views of FIG. 1 aa 'direction and FIG. 3 according to an embodiment of the present invention. (a) to FIG. 3 (d) are process cross-sectional views in the first direction bb ′ in accordance with one embodiment of the present invention, and FIG. 4 is a plan view of the second (d) and third (c) views.

Claims (3)

반도체 소자의 설계시 최소 디자인 룰을 어길 수 밖에 없는 조밀한 지역에서 상부 도전체 콘택홀과 하부 도전체와의 오버랩여유를 제조공정시 확보하게 하는 반도체 소자의 콘택홀 오버랩여유 확보방법에 있어서, 실리콘 기판(1)상에 소자분리 산화막(2)을 형성한 다음 제1절연막(3)을 형성하여 절연 및 평탄화 한 다음, 하부 도전체 라인 마스크(4a)를 사용하여 하부 도전체 라인(4)을 형성하는 제1단계, 상기 구조 상부에 질화절연막(5)을 형성한 다음, 오버랩 확보용 마스크(7a)를 사용하여 오버랩 확보용 마스크의 감광막패턴(7)을 형성한 다음 상기 감광막(7)을 이용하여 질화절연막(5)을 식각한 후, 감광막(7)을 제거하는 제2단계, 상기 하부도전체 라인(4) 상부에만 선택적 텅스텐(8)을 증착하는 제3단계 및, 제3절연막(9)을 형성하여 평탄화 한 다음, 상부 도전체 콘택홀 마스크(10a)를 이용하여 상부 도전체 콘택홀(10)을 형성하는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 오버랩여유 확보방법.In the method of securing the contact hole overlap margin of the semiconductor device to ensure the overlap margin between the upper conductor contact hole and the lower conductor in the manufacturing process in a dense area where the minimum design rule must be violated in the design of the semiconductor device. After the device isolation oxide film 2 is formed on the substrate 1, the first insulating film 3 is formed to be insulated and planarized, and then the lower conductor line 4 is formed using the lower conductor line mask 4a. In the first step of forming, the nitride insulating film 5 is formed on the structure, and then the photosensitive film pattern 7 of the overlap securing mask is formed using the overlap securing mask 7a. After etching the nitride insulating film 5 by using the second step of removing the photoresist film 7, a third step of depositing selective tungsten 8 only on the lower conductive line 4, and a third insulating film ( 9) to form and planarize, and then top conductive Contact holes overlap margin secured a semiconductor element by using a contact hole mask (10a) comprising the fourth step of forming an upper conductive contact hole 10. 제1항에 있어서, 상기 제2단계는 상기 질화절연막(5) 형성후, 제2절연막(6)을 형성하여 평탄화 한 다음, 오버랩 확보용 마스크(7a)를 사용하여 오버랩 확보용 마스크의 감광막패턴(7)을 형성한 후, 제2절연막(6), 질화절연막(5)을 건식식각하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 오버랩여유 확보방법.The method of claim 1, wherein in the second step, after the nitride insulating film 5 is formed, the second insulating film 6 is formed and planarized, and then the photoresist film pattern of the overlap securing mask is formed using the overlap securing mask 7a. And forming dry etching of the second insulating film (6) and the nitride insulating film (5) after forming (7). 제1항에 있어서, 상기 제3단계의 선택적 텅스텐의 증착두께를 0.15마이크로미터 이상이 되도록 하되, 간격이 하부 도전체 라인 간의 간격이 되도록 유지해 주어 상기 하부 도전체 라인(4)간의 직접적 단락을 막는 것을 특징으로 하는 반도체 소자의 콘택홀 오버랩여유 확보방법.The method of claim 1, wherein the deposition thickness of the selective tungsten in the third step is 0.15 micrometers or more, while maintaining the spacing between the lower conductor lines to prevent direct short circuit between the lower conductor lines (4). A method for securing contact hole overlap margin of a semiconductor device, comprising: ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930010827A 1993-06-14 1993-06-14 Over lap margin securing method of semiconductor device KR970000693B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930010827A KR970000693B1 (en) 1993-06-14 1993-06-14 Over lap margin securing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930010827A KR970000693B1 (en) 1993-06-14 1993-06-14 Over lap margin securing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950001895A true KR950001895A (en) 1995-01-04
KR970000693B1 KR970000693B1 (en) 1997-01-18

Family

ID=19357383

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930010827A KR970000693B1 (en) 1993-06-14 1993-06-14 Over lap margin securing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR970000693B1 (en)

Also Published As

Publication number Publication date
KR970000693B1 (en) 1997-01-18

Similar Documents

Publication Publication Date Title
KR950000660B1 (en) Fine patterning method for high density integrated circuit device
KR950034492A (en) Direct Wafer Bonding Structure and Manufacturing Method Thereof
KR970077744A (en) Thin film transistor and manufacturing method thereof
US5286673A (en) Method for forming position alignment marks in a manufacturing SOI device
US5924006A (en) Trench surrounded metal pattern
KR940022801A (en) Contact formation method of semiconductor device
KR100220297B1 (en) Method of forming contact in mutilayered structure of semiconductor device
KR890011035A (en) Integrated circuit manufacturing method and electrical connection forming method
KR950001895A (en) Method of securing contact hole overflow margin of semiconductor device
KR0179838B1 (en) Structure of insulating film semiconductor device and method of planarizing insulating film
KR920005338A (en) Semiconductor device manufacturing method
KR100245091B1 (en) Process for forming interconnector of semiconductor device
KR100248150B1 (en) Method of forming contact hole in semiconductor device
KR100366612B1 (en) Method for manufacturing semiconductor device having flat field isolation layer
KR970017961A (en) Semiconductor integrated circuit device and manufacturing method thereof
KR100738577B1 (en) Method of contact in semiconductor device
KR19980031103A (en) Manufacturing method of semiconductor device
KR960006703B1 (en) Wire manufacturing method of semiconductor device
KR100399934B1 (en) Method for forming contact of semiconductor device
KR100351892B1 (en) Forming method for multilayer interconnection
JPH0595048A (en) Manufacture of semiconductor integrated circuit device
KR20020031491A (en) A dummy capacity using dummy pattern and forming method thereof
KR0140729B1 (en) A method form of fine contact
JPH0936222A (en) Semiconductor device and its manufacture
KR19990065705A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101224

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee