KR950001412A - Method for forming fine line width pattern of semiconductor device using antireflective layer - Google Patents

Method for forming fine line width pattern of semiconductor device using antireflective layer Download PDF

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Publication number
KR950001412A
KR950001412A KR1019930012205A KR930012205A KR950001412A KR 950001412 A KR950001412 A KR 950001412A KR 1019930012205 A KR1019930012205 A KR 1019930012205A KR 930012205 A KR930012205 A KR 930012205A KR 950001412 A KR950001412 A KR 950001412A
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South Korea
Prior art keywords
layer
line width
fine line
semiconductor device
forming
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KR1019930012205A
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Korean (ko)
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KR970007436B1 (en
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권오성
김진태
홍흥기
백동원
김세정
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김주용
현대전자산업 주식회사
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Priority to KR1019930012205A priority Critical patent/KR970007436B1/en
Publication of KR950001412A publication Critical patent/KR950001412A/en
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Publication of KR970007436B1 publication Critical patent/KR970007436B1/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 단일 포토레지스트와 무반사 층을 이용한 반도체 소자의 미세선폭 패턴 형성방법법에 있어서, 패턴을 형성할 반사층(2) 상에 LPCVD(Low Pressure Chemical Vapor Deposition) 증착법에 의한 무반사층(3)을 형성하되 상기 반사층(2)과 무반사층(3) 그리고 이후에 증착될 포토레지스트층(4) 각각의 굴절률 및 노광시키는 빛의 파장을 고려하여 소정의 두께로 증착하는 단계와; 상기 무반사층(3) 상에 단일 포토레지스트층(4)을 증착하는 단계를 포함하여 이루어지는 것을 특징으로 하는 무반사 층을 이용한 반도체 소자의 미세선폭 패턴 형성방법에 관한 것이다.In the method of forming a fine line width pattern of a semiconductor device using a single photoresist and an antireflective layer, the antireflective layer 3 by LPCVD (Low Pressure Chemical Vapor Deposition) deposition is formed on a reflective layer 2 to form a pattern. Forming and depositing to a predetermined thickness in consideration of the refractive index of each of the reflective layer (2) and the anti-reflective layer (3) and the photoresist layer (4) to be subsequently deposited and the wavelength of light to be exposed; It relates to a method for forming a fine line width pattern of a semiconductor device using an antireflection layer, characterized in that it comprises the step of depositing a single photoresist layer (4) on the antireflection layer (3).

따라서 본 발명은, 단일층 포토레지스트를 이용한 미세선폭 형성시 발생하는 반사파로 인한 정체파 및 노치현상을 막을 수 있고, 또한 충분한 노광을 할 수 있기 때문에 포토레지스트의 스컴(scum)을 줄이게 되어 넓은 범위의 미세선폭을 형성할 수 있는 효과가 있다.Accordingly, the present invention can prevent stagnant waves and notches due to reflected waves generated when forming a fine line width using a single layer photoresist, and can also expose sufficient exposure, thereby reducing the scum of the photoresist, thereby providing a wide range. There is an effect that can form a fine line width.

Description

무반사 층을 이용한 반도체 소자의 미세선폭 패턴 형성방법Method for forming fine line width pattern of semiconductor device using antireflective layer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 단일 포토레지스트를 사용한 패턴 형성 작용 상태도, 제4도는 제3도의 포토공정을 통한 패턴 형성 공정도이다.FIG. 3 is a pattern forming state diagram using a single photoresist according to the present invention, and FIG. 4 is a pattern forming process diagram through the photo process of FIG.

Claims (4)

단일 포토레지스트와 무반사층을 이용한 반도체 소자의 미세선폭 패턴 형성방법에 있어서, 패턴을 형성할 반사층(2) 상에 LPCVD(Low Pressure Chemical Vapor Deposition) 증착법에 의한 무반사층(3)을 형성하되 상기 반사층(2)과 무반사층(3) 그리고 이후에 증착될 포토레지스트층(4) 각각의 굴절률 및 노광시키는 빛의 파장을 고려하여 소정의 두께로 증착하는 단계와; 상기 무반사층(3) 상에 단일 포토레지스트층(4)을 증착하는 단계를 포함하여 이루어지는 것을 특징으로 하는 무반사층을 이용한 반도체 소자의 미세선폭 패턴 형성방법.In the method for forming a fine line width pattern of a semiconductor device using a single photoresist and an antireflective layer, an antireflective layer (3) by LPCVD (Low Pressure Chemical Vapor Deposition) deposition is formed on a reflective layer 2 on which a pattern is to be formed. Depositing to a predetermined thickness in consideration of the refractive index of each of (2) and the antireflective layer (3) and the photoresist layer (4) to be subsequently deposited and the wavelength of light to be exposed; And depositing a single photoresist layer (4) on the antireflective layer (3). 제1항에 있어서, 상기 반사층(2)은 폴리실리콘막인 것을 특징으로 하는 무반사층을 이용한 반도체 소자의 미세선폭 패턴 형성방법.The method of forming a fine line width pattern of a semiconductor device using an antireflection layer according to claim 1, wherein the reflective layer (2) is a polysilicon film. 제1항에 있어서, 상기 무반사층(3)의 굴절률(n2)은 상기 반사층(2)의 굴절률(n1)과 단일 포토레지스트층(4)의 굴절률(n3)의 곱의 값에 대한 제곱근 값을 굴절률로 하는 것을 특징으로 하는 무반사층을 이용한 반도체 소자의 미세선폭 패턴 형성방법.The method of claim 1, wherein the refractive index (n 2) of the anti-reflection layer 3 is about the value of a product of a refractive index (n 3) of the refractive index (n 1) and a single photoresist layer (4) of the reflective layer (2) A method of forming a fine line width pattern of a semiconductor device using an antireflection layer, wherein the square root value is a refractive index. 제3항에 있어서, 상기 무반사층(3)의 증착 두께는 굴절률(n2)에 반비례하고 빛의 파장의 홀수배에 비례하도록 하는 것을 특징으로 하는 무반사층을 이용한 반도체 소자의 미세선폭 패턴 형성방법.The method of claim 3, wherein the deposition thickness of the antireflective layer 3 is inversely proportional to the refractive index n 2 and proportional to an odd number of wavelengths of light. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930012205A 1993-06-30 1993-06-30 Pattern formation of semiconductor element using non-reflecting layer KR970007436B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930012205A KR970007436B1 (en) 1993-06-30 1993-06-30 Pattern formation of semiconductor element using non-reflecting layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930012205A KR970007436B1 (en) 1993-06-30 1993-06-30 Pattern formation of semiconductor element using non-reflecting layer

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KR950001412A true KR950001412A (en) 1995-01-03
KR970007436B1 KR970007436B1 (en) 1997-05-08

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