KR950000454Y1 - Circuit for protecting jittering in television set - Google Patents

Abstract

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Description

TV screen jitter prevention circuit

1 is a conventional TV synchronization signal processing circuit diagram.

2 is a synchronization signal processing circuit diagram of a TV screen jitter prevention circuit of the present invention.

* Explanation of symbols for main parts of the drawings

101, 202: Synchronous separation unit 115, 217: Vertical deflection driving unit

116, 218: horizontal deflection driving unit 110, 212: image signal processing unit

111, 214: video signal output unit 210: horizontal synchronization unit

The present invention relates to a TV synchronization signal processing circuit, and more particularly, to a TV screen jitter prevention circuit for preventing jitter of the screen caused by the vibration of the deflection in the TV or monitor system.

In the conventional TV synchronization signal processing circuit, as shown in FIG. 1, the image signal is input to the input terminal IN and the oscillation frequency is input from the oscillator 102 to synchronize the horizontal synchronization signal and the vertical synchronization signal. A separation unit 101, a vertical deflection driving unit 115 that receives a vertical synchronization signal from the synchronization separation unit 101, and performs a vertical deflection; and a horizontal synchronization signal from the synchronization separation unit 101; The horizontal deflection driving unit 116 deflects and the image signal is inputted from the input terminal IN, and the horizontal synchronization signal from the synchronization separating unit 101 through the horizontal buffer unit 108 and the vertical buffer unit 109, respectively. And a video signal processor 110 for receiving a vertical synchronous signal and processing the video signal, and receiving a video signal from the video signal processor 110 and receiving a horizontal synchronous signal and a vertical synchronous signal from the sync separator 101. Video signal output to receive and output video signal It consists of 111.

The operation of the conventional circuit is described in detail with reference to FIG. 1 as follows.

When the video signal is input from the input terminal IN and the 34fH oscillation frequency is input from the oscillator 102, the sync separator 101 separates the horizontal sync signal and the vertical sync signal from the input video signal. The vertical synchronizing signal separated by the synchronizing separation unit 101 is intended to be put into the vertical deflection driving unit 115 including the vertical driving unit 103, the vertical deflection unit 104, and the vertical alternating current / direct current feedback unit 105. It is used for driving and is input to the image signal processing unit 110 through the vertical buffer unit 109 to control the timing and is input to the image signal output unit 111 to be used as a vertical blanking signal.

The horizontal synchronizing signal separated by the synchronization separating unit 101 is input to the horizontal deflection driving unit 116 including the horizontal driving unit 106 and the horizontal deflection unit 107 and used for the horizontal deflection driving, and to the image signal processing unit 110. It is input through the horizontal buffer unit 108 to control timing and is also input to the image signal output unit 111.

In addition, the feedback is received from the vertical deflection unit 104 for vertical gain and position linearity, and the AC and DC current is controlled in the vertical AC / DC feedback unit 105 to feed back to the vertical driving unit 103.

In the system of synchronous separation by oscillating to 32, the oscillation frequency is locked to the horizontal synchronous signal separated from the image by fH which is divided by 32, and the locking phase is controlled by AFC (Auto Frequency Control). .

For this AFC, a horizontal blanking (H-BLK) (usually a FLYBACK pulse) is fed back to the synchronization separating unit 101 in the horizontal deflection unit 107.

However, in the conventional circuit configured as described above, in the synchronous separation system composed of 32 fH of the synchronous separation unit, the F's speed is required to follow the vertical synchronous signal period, so it is unable to follow the horizontal drive signal that slightly floats in the vertical synchronous signal period. If the horizontal sync signal is slightly shaken, the horizontal sync and vertical sync should be adjusted to match the shake of the horizontal sync signal in the video signal processing unit and the video signal output unit, but it is possible to prevent the shaking of the CRT. Although the feedback terminal has a high speed, the horizontal synchronization of the output terminal cannot follow the horizontal period, which causes jitter on the CRT screen due to the vibration of the deflection.

The present invention, in view of the problems of the conventional circuit, the synchronization signal by using the ACC pulse, which shows the vibration of the deflection without using the synchronization separator and the flyback of the deflection for the horizontal and vertical synchronization signals used for the image. The TV screen jitter prevention circuit used as a horizontal and vertical synchronous signal used for image processing by generating a digital signal will be described in detail with reference to the accompanying drawings.

In the TV jitter prevention circuit of the present invention, as shown in FIG. 2, an image signal is inputted from a signal detector 209 which turns on the switch 201 when a signal is turned on and off when a signal is not signaled, and an input terminal IN. When the oscillation frequency is input from the oscillator 203, the synchronous separator 202 outputs a horizontal synchronous signal and a vertical synchronous signal, and a vertical deflection for receiving a vertical synchronous signal from the synchronous separator 202 for vertical deflection. The driving unit 217, the horizontal deflection driving unit 218 which receives the horizontal synchronizing signal from the synchronizing separation unit 202, and performs horizontal deflection, and the signal is received from the horizontal deflection driving unit 218 and the synchronizing separation unit 202. The horizontal synchronous signal 210 receives the horizontal synchronous signal, the vertical synchronous signal, and the video signal from the horizontal synchronous part 210, the synchronous separator 202, and the input terminal IN, respectively, and outputs a signal to the horizontal synchronous signal. A video signal processor 212 and the video No. video signal and horizontally from the processing unit 212. The video signal consists of the output unit 214 via a vertical synchronization processing unit receives the horizontal and vertical sync signals and outputs the video signal.

Referring to Figure 2 with reference to the operation of the present TV screen jitter prevention circuit as follows.

When a video signal is input to the input terminal IN, a locked synchronization signal is used, and when there is no signal, a signal of the signal detection unit 209 is used to use a free running synchronization signal of the synchronization separation unit 202. As the detection signal, the switch 201 is turned on or off to input the video signal to the synchronization separator 202 at the time of the idle signal, but not to input the non-signal.

In addition, the synchronizing separator 202 divides the oscillation frequency input from the oscillator 203 by 32 to generate a horizontal synchronizing signal, and counts the horizontal synchronizing signal to generate a vertical synchronizing signal, and the vertical synchronizing signal is connected to the vertical driving unit 204. It is input to the vertical deflection driving unit 217 composed of the vertical deflection unit 205 and the vertical alternating current / direct current feedback 206 and used for vertical deflection driving. The horizontal synchronous signal is composed of the horizontal driving unit 207 and the horizontal deflection unit 208. It is input to the horizontal driving unit 218 and used for the horizontal deflection driving.

The synchronization terminal 203 divides the oscillation into 32 generated in the oscillation unit 203, locks the horizontal and vertical signals, and hangs the horizontal and vertical synchronizing units.

The role of the AFC terminal is to determine the phase (i.e., time) at which point in locking the horizontal and vertical signals generated by dividing the signal's horizontal, vertical, and oscillation frequencies.

However, since the FPC speed is usually in the vertical period, the vibration of the deflection (change in the horizontal synchronizing signal) remains as it is in the AFC terminal of the synchronizing separator 202, but the horizontal synchronizing signal of the synchronizing separator 202 follows the vertical signal period. Goes. In this case, the vertical synchronizing signal follows the vertical signal period and there is no problem.

When the image is displayed on the CRT, the vibration of the deflection is represented by the image (jitter) of the deflection, so the deflection of the deflection is compensated by the image signal processing unit 212 and the image signal output unit 214. A horizontal synchronous signal of the horizontal synchronous unit 210 is generated by using the AFC voltage at the AFC terminal of 202.

The horizontal deflection driving unit 218, the horizontal deflection driving unit 208, and the flyback transformer (FBT) obtain a horizontal Fryback voltage for the AFC pulses. It is applied to the AFC terminal of the synchronization separating unit 202 via C1). The transistor Q1 and the resistor R4 are AC-coupled by the capacitor C1 of the horizontal synchronization unit 210 and inverted without changing the DC value of the AFC pulse inputted to the ACC terminal of the synchronous separation unit 202. ) Was used.

The voltage at point (a) A differential amplifier consisting of transistors Q2 and Q3 is set by adjusting the resistance value to operate in the active region. The values of the resistors R6 and R10 are the same so that the transistor Q2 base voltage Vb and the transistor Q3 base voltage Vc are the same voltage.

Therefore, when the base voltages of the transistors Q2 and Q3 are equal to each other and the base potential of the transistor Q2 is 0.6 volts less than the emitter potential, the transistor Q2 becomes conductive. When the transistor Q2 is turned on, the signal input to the base is inverted and output to the collector of the transistor Q3. Therefore, when the AFC pulse input to the transistor Q1 is output to the collector and then to the base of the transistor Q3, the transistor Q3 outputs a horizontal synchronous signal to the collector.

By using the inventive circuit configured as described above, there is an effect of preventing jitter of the screen due to the vibration of the deflection in the TV or monitor system.

Claims (1)

The video signal is input from the signal detecting unit 209 and the input terminal IN, and the oscillation frequency is input from the oscillation unit 203. And a horizontal deflection driver 217 for outputting a horizontal synchronous signal and a vertical synchronous signal, a vertical deflection driver 217 for vertically deflecting the vertical synchronous signal from the synchronous separation part 202, and the synchronous separation part. A horizontal deflection driver 218 for receiving a horizontal synchronous signal from the horizontal deflection driver 218, and a horizontal deflection driver 218 for outputting an AFC signal to the synchronization separator 202; And a horizontal synchronous unit 210 for generating a horizontal synchronous signal, a vertical buffer unit 211 for buffering the vertical synchronous signal output from the synchronous separator 202, and the horizontal synchronous unit 210 and a vertical unit 211. And horizontal synchronization signal from input terminal (IN) The video signal processor 212 receives the direct sync signal and the video signal and processes the video signal, and the horizontal and vertical sync signals are transmitted from the video signal processor 212 through the video signal and the horizontal and vertical sync processor 213. TV screen jitter prevention circuit comprising a video signal output unit 214 for receiving an input and outputting a video signal.