KR950000153B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR950000153B1 KR950000153B1 KR1019920004657A KR920004657A KR950000153B1 KR 950000153 B1 KR950000153 B1 KR 950000153B1 KR 1019920004657 A KR1019920004657 A KR 1019920004657A KR 920004657 A KR920004657 A KR 920004657A KR 950000153 B1 KR950000153 B1 KR 950000153B1
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- gate electrode
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- polysilicon
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- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 claims description 3
- 229910021352 titanium disilicide Inorganic materials 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000007943 implant Substances 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000000047 product Substances 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제 1a 도 내지 제 1d 도는 종래 방법에 의한 폴리사이드 게이트 형성방법을 도시한 공정순서 단면도.1A to 1D are cross-sectional views of a process sequence showing a polyside gate forming method according to a conventional method.
제 2a 도 내지 제 2g 도는 본 발명의 방법에 의한 일실시예의 폴리사이드 게이트 형성방법을 도시한 공정순서 단면도.2A to 2G are cross-sectional views of a process sequence showing a method for forming a polyside gate according to an embodiment of the present invention.
제 3a 도 내지 제 3b 도는 폴리사이드 게이트 위에 O3TEOS막을 형성하여서 자기정렬 접촉창을 형성하는 방법을 도시한 본 발명의 공정순서 단면도.3A to 3B are cross-sectional views of a process sequence of the present invention showing a method of forming a self-aligned contact window by forming an O 3 TEOS film on a polyside gate.
본 발명은 반도체 메모리장치의 제조방법에 관한 것으로, 특히 폴리사이드 게이트(Poly Cide Gate) 전극 및 자기정렬 접촉창 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a polyside gate electrode and a self-aligning contact window.
최근, 반도체 메모리장치의 초고집적화로 인해 배선의 폭은 좁아지고, 배선길이는 더 길어짐에 따라 배선저항이 더욱 증가되므로 연결배선으로서 확산된 단결정 실리콘이나 고농도의 폴리실리콘을 사용하는데는 큰 제약이 따르고 있다.Recently, due to the ultra-high integration of semiconductor memory devices, the wiring width is narrowed and the wiring length is further increased as the wiring length becomes longer. Therefore, the use of diffused single crystal silicon or high concentration polysilicon as a connection wiring has great limitations. have.
따라서 초고집적회로에 있어서 배선연결은 미래에 가장 필요한 기술분야의 하나가 되고 있는데, MOS 소자에서의 상기 문제에 관한 해결책은 폴리실리콘 게이트물질을 대체하거나 보충할만한 고전도도 물질의 개발이다.Thus, wiring connections in ultra-high integrated circuits have become one of the most necessary technical fields in the future, and the solution to the above problem in MOS devices is the development of high conductivity materials to replace or supplement polysilicon gate materials.
이러한 목적에 사용하기 위하여 고전도의 내화성 금속 실리사이드가 이용되고 있는데 상기 고전도의 물질은 고온에서의 안정성, 건식식각의 가능성, 산화성 등의 물질 특성이 구비되어야 한다.A high conductivity refractory metal silicide is used for this purpose. The high conductivity material should be provided with material properties such as stability at high temperature, possibility of dry etching, and oxidation resistance.
그러나, 게이트의 안정성 및 산화성, 실리사이드와 산화막 사이의 접착력 등이 제조공정에 있어서 큰 어려움이 되고 있다.However, the stability and oxidization of the gate, the adhesive force between the silicide and the oxide film, etc. are a great difficulty in the manufacturing process.
종래의 폴리사이드 게이트의 형성공정은 실질적으로 폴리실리콘 게이트공정과 동일하나, 게이트전극재료로 폴리실리콘층과 실리사이드층이 연속적으로 증착되고 상기 실리사이드를 균질화하기 위해 고온처리하는 점이 다르다.The process of forming a conventional polyside gate is substantially the same as a polysilicon gate process, except that a polysilicon layer and a silicide layer are successively deposited as a gate electrode material and subjected to a high temperature treatment to homogenize the silicide.
제 1a 도 내지 제 1d 도는 종래의 폴리사이드 게이트전극의 형성방법을 도시한 공정순서도로서, 먼저, 반도체기판(100) 상에 게이트산화막(11), 폴리실리콘막(12) 및 티타늄디실리사이드막(15)을 순차로 형성시킨다.(제 1a 도). 그 다음, 상기 적층된 막(11, 12, 15)을 사진식각공정에 의해 게이트전극패턴(1G)을 형성시킨다. 이때 식각공정시 게이트산화막(11)의 엣지부근(11a)이 손상되거나 얇아져 게이트산화막의 항복전압이 낮아지게 되고 또한, 티타늄디실리사이드층(15) 물질 특성으로 인해 폴리실리콘막(12)의 윤곽이 사다리꼴 모양으로 더욱 포지티브경사를 이루게 되며, 반도체기판(100)이 피팅(pitting)되어 활성영역에서 동작시 누설전류의 증가요인이 되는 문제점이 있다(제 1b 도). 그 다음에 850℃ 이상의 건식 O2분위기에서 상기 결과물의 표면에 산화층(14)을 형성시킴으로서 게이트산화막(11)의 엣지부근(11a)이 식각으로 손상되어 얇아진 것을 보상하게 되나, 여전히 폴리실리콘막의 윤곽 및 반도체기판의 피팅문제는 해결되지 못하고 있다.(제 1c 도) 그 다음에, 상기 표면산화층 형성공정에 이어서 기판 전면에 CVD(Chemical Vapor Depositin) 산화막을 형성시킨 후, 계속해서 이방성 식각법에 의해 게이트전극패턴(1G) 측벽에 산화막 스페이서(16)를 형성시키고, 상기 스페이서를 이용하여 불순물을 활성영역에 이온주입시킨 다음, 소오스/드레인영역(17)을 형성시킨다(제 1d 도).1A to 1D are process flowcharts showing a conventional method for forming a polyside gate electrode. First, a gate oxide film 11, a polysilicon film 12, and a titanium disilicide film (on a semiconductor substrate 100) are described. 15) are formed sequentially (FIG. 1a). Then, the stacked layers 11, 12, and 15 are formed by the photolithography process to form the gate electrode pattern 1G. At this time, the edge region 11a of the gate oxide layer 11 is damaged or thinned during the etching process, thereby lowering the breakdown voltage of the gate oxide layer. Also, the polysilicon layer 12 has a contoured material due to the material properties of the titanium dissilicide layer 15. The trapezoidal shape is more positively inclined, and the semiconductor substrate 100 is pitting to increase the leakage current when operating in the active region (FIG. 1b). Then, by forming the oxide layer 14 on the surface of the resultant product in a dry O 2 atmosphere of 850 ° C. or higher, the edge portion 11a of the gate oxide film 11 is etched to be damaged and thinned, but the polysilicon film is still outlined. The problem of fitting the semiconductor substrate is not solved. (Fig. 1C) Next, after forming the surface oxide layer, a CVD (Chemical Vapor Depositin) oxide film is formed on the entire surface of the substrate, followed by anisotropic etching. An oxide spacer 16 is formed on the sidewall of the gate electrode pattern 1G, and impurities are implanted into the active region using the spacer, and then a source / drain region 17 is formed (FIG. 1D).
그러나, 이와 같은 종래 방법에 의하면 폴리실리콘막의 윤곽이 사다리꼴 모양의 포지티브경사를 이루게 되어 소망하는 게이트전극형태를 만들 수 없으며, 반도체기판이 손상되는 피팅문제를 해결할 수 없을 뿐만아니라, 오히려 폴리사이드 적층구조 형성후 게이트 폴리실리콘 산화막 형성공정 및 CVD 산화막의 리플로우(Reflow) 공정중에 850℃ 이상의 고온열처리를 함으로서 티타늄디실리사이드막(15)의 티타늄원자가 폴리실리콘막(12)의 그레인 경계를 따라 하방으로 확산되어 게이트산화막(11)까지 확산되어 게이트산화막의 항복특성을 열화시키는 문제점이 있다.However, according to this conventional method, the contour of the polysilicon film forms a trapezoidal positive inclination, which does not form a desired gate electrode shape, and it does not solve the problem of fitting that damages the semiconductor substrate. After formation, high temperature heat treatment of 850 ° C. or higher during the gate polysilicon oxide film formation process and the reflow process of the CVD oxide film causes the titanium atoms of the titanium dissilicide film 15 to diffuse downward along the grain boundaries of the polysilicon film 12. As a result, the gate oxide film 11 is diffused to the gate oxide film 11, thereby degrading the yield characteristic of the gate oxide film.
따라서, 본 발명의 목적은 종래 방법에 의한 폴리사이드 게이트전극 식각시 폴리실리콘막의 윤곽이 포지티브경사를 이루게 되고 반도체기판의 피팅으로 인해 활성영역이 손상되는 것을 방지하는 폴리사이드 게이트전극의 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a method of forming a polyside gate electrode in which the contour of the polysilicon layer forms a positive slope during the etching of the polyside gate electrode by a conventional method and prevents damage to the active region due to fitting of the semiconductor substrate. There is.
본 발명의 다른 목적은 고온열처리공정에 의해 티타늄디실리사이드막에 열손상이 가해지는 것을 방지할 수 있는 폴리사이드 게이트전극의 형성방법을 제공하는 데 있다.Another object of the present invention is to provide a method for forming a polyside gate electrode capable of preventing thermal damage to the titanium dissilicide film by a high temperature heat treatment process.
상기 목적을 달성하기 위하여 본 발명의 폴리사이드 게이트전극의 형성방법에 있어서, 반도체기판상에 게이트산화막, 폴리실리콘막 및 질화막을 순차적으로 형성시키는 공정, 상기 적층된 막들을 사진식각공정에 의해 게이트전극패턴을 형성시킨 다음, 게이트산화막과 폴리실리콘막을 산화시키는 공정, 상기 결과물의 표면에 침적산화물을 형성시킨 다음, 상기 침적산화물을 이방성 식각하여 게이트전극패턴 측벽에 스페이서를 형성시키는 공정, 이어서 상기 스페이서 형성 후 활성영역에 불순물을 이온주입하여 소오스/드레인영역을 형성시킨 다음, 활성영역위의 실리콘을 열산화시키는 공정, 상기 열산화막 형성후 게이트전극패턴 상부의 질화막을 제거시키는 공정, 계속해서 상기 결과물 전면에 티타늄을 침적시켜서 1차 어닐(Anneal) 공정을 통해 티타늄디실리사이드층을 형성시키고 난 다음, 습식식각공정에 의해서 폴리실리콘 위에만 실리사이드층을 형성시킨 후 2차 어닐하는 공정을 구비하여서 이루어진 것을 특징으로 한다.In order to achieve the above object, in the method of forming a polyside gate electrode of the present invention, a step of sequentially forming a gate oxide film, a polysilicon film, and a nitride film on a semiconductor substrate, and the stacked films of the gate electrode by a photolithography process Forming a pattern, then oxidizing the gate oxide film and the polysilicon film, forming a deposited oxide on the surface of the resultant, and then anisotropically etching the deposited oxide to form a spacer on the sidewall of the gate electrode pattern, followed by forming the spacer. And implanting impurities into the active region to form a source / drain region, and then thermally oxidizing silicon on the active region, removing the nitride layer on the gate electrode pattern after forming the thermal oxide layer, and then continuing the entire surface of the resultant. By depositing titanium in the first annealing process Other nyumdi I and forming a silicide layer characterized by comprising a step of hayeoseo secondary annealing after forming a silicide layer over the polysilicon only by the following, a wet etching process.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 2a 도 내지 제 2g 도는 본 발명의 방법에 의한 일시예로서, 먼저 제 2a 도를 참조하면, 반도체기판(200) 위에 게이트산화막(21), 폴리실리콘(22) 및 100∼500Å 정도의 질화막(23)을 순차로 적층 형성시킨다.2A to 2G are temporary examples of the method of the present invention. Referring first to FIG. 2A, a gate oxide film 21, a polysilicon 22, and a nitride film having a thickness of about 100 to 500 mV on a semiconductor substrate 200 are described. 23) are sequentially laminated.
제 2b 도를 참조하면, 포트리소그라피 기술을 이용하여 상기 적층 결과물 위에 게이트전극을 패터닝하고, 이방성 식각법으로 게이트전극(2G)을 형성시킨 다음, 게이트산화막(21)의 엣지부근(21A)이 손상된 것을 보상하기 위해서 건식 O2분위기의 산화공정에 의해 제1열산화막(24)이 형성한다.Referring to FIG. 2B, a gate electrode is patterned on the stacked product by using a photolithography technique, a gate electrode 2G is formed by anisotropic etching, and then the edge portion 21A of the gate oxide film 21 is damaged. In order to compensate for this, the first thermal oxide film 24 is formed by an oxidation process in a dry O 2 atmosphere.
제 2c 도를 참조하면, 상기 결과물 위에 침적공정을 통해서 고온열산화물(high Temperature Oxide; HTO)인 침적산화물(26)을 형성시킨 다음, 이방성 식각법에 의해 상기 침적산화물을 식각시킴으로서, 제 2d 도에서처럼 스페이서(26a)를 형성시킬 수 있게 된다.Referring to FIG. 2C, by forming an immersion oxide 26, which is a high temperature oxide (HTO), through the deposition process on the resultant, and then etching the deposited oxide by anisotropic etching, FIG. As in the spacer 26a can be formed.
제 2e 도를 참조하면, 활성영역 위에 불순물을 이온주입하여 소오스/드레인영역(27)을 형성시킨 다음, 후속공정인 티타늄 침적공정시 활성영역 위에서 실리사이드화가 진행되는 것을 방지하기 위하여 산화공정에 의해 100∼300Å 정도의 제2열산화막(28)을 형성시킨다. 이때, 게이트전극패턴(2G) 위에는 질화막(23)이 존재하여 산화공정시 상기 폴리실리콘막(22)은 산화되지 않게 된다.Referring to FIG. 2E, impurities are implanted into the active region to form the source / drain region 27, and then 100 may be oxidized to prevent silicide formation on the active region during the subsequent titanium deposition process. A second thermal oxide film 28 of about 300 kPa is formed. At this time, the nitride film 23 is present on the gate electrode pattern 2G, so that the polysilicon film 22 is not oxidized during the oxidation process.
제 2f 도를 참조하면, 상기 질화막(23)을 습식식각법에 의해 제거하여 상기 폴리실리콘막(22)을 노출시킨 다음, 상기 결과물 전면에 티타늄을 500∼1000Å 정도 침적시켜 이어서, 티타늄 침적층(25)을 형성시킨다.Referring to FIG. 2F, the nitride film 23 is removed by a wet etching method to expose the polysilicon film 22, and then titanium is deposited on the entire surface of the resultant by about 500 to 1000 mm, followed by a titanium deposition layer ( 25).
제 2g 도를 참조하면, 상기 티타늄 침적층(25)을 500∼700℃ 정도의 저온공정인 RTA(Rapid Thermal Anneal) 도는 FA(Furnace Anneal) 공정 등으로 1차 어닐(Aunneal)을 실시하여 폴리사이드층(22)과 반응시켜 티타늄 디실리사이드층(25a)을 형성시킨 다음, 계속해서 선택식각액인 SC1(H2O2: NH4OH : H2O=1:1:5)으로 스페이서 및 활성영역위 산화막부위의 미반응 티타늄 침적층(25)을 식각시킨다. 상기 식각공정 다음으로 상기 폴리실리콘 위의 티타늄디실리사이드층(25a)을 700∼900℃ 정도의 RTA 또는 FA 고온공정으로 2차 어닐을 실시하여 폴리사이드게이트(29) 형성공정을 완성시킨다.Referring to FIG. 2g, the titanium deposition layer 25 is poly-sintered by performing primary annealing in a rapid thermal annealing (RTA) or a furnace annealing (FA) process, which is a low temperature process of about 500 to 700 ° C. After reacting with layer 22 to form a titanium disilicide layer 25a, the spacer and the active region were then continued with SC1 (H 2 O 2 : NH 4 OH: H 2 O = 1: 1: 5), which is a selective etching solution. The unreacted titanium deposition layer 25 on the oxide layer is etched. After the etching process, the titanium dissilicide layer 25a on the polysilicon is second annealed by RTA or FA high temperature process at about 700 to 900 ° C to complete the process of forming the polyside gate 29.
제 3a 도 내지 제 3b 도는 본 발명의 방법을 이용한 다른 실시예로서 본 발명의 폴리사이드 게이트 결과물 (제 2a 도∼제 2g 도) 위에 O3TEOS(Tetra Ethyle Ortho Silicate) USG(Undoped Silicate Glass ; 39)막을 이용하여 침적시키게 되면, 침적률이 실리사이드에서는 산화막보다 2배 정도 빠르게 침적되므로 이방성 식각을 이용하면 자기 정렬 비트(bit)선 접촉창 및 매몰 접촉창을 형성시킬 수가 있다.3a to 3b show another embodiment using the method of the present invention on the polyside gate product of the present invention (FIGS. 2a to 2g), O 3 TEOS (Tetra Ethyle Ortho Silicate) Undoped Silicate Glass (USG) 39 When deposited using a film, the deposition rate is deposited about twice as fast as the oxide film in silicide, so that anisotropic etching can form a self-aligned bit line contact window and a buried contact window.
따라서 상술한 본 발명의 방법에 의하면, 게이트산화막(21) 및 폴리실리콘(22) 산화공정과 침적산화물(20) 형성공정 등 고온열산화공정을 티타늄디실리사이드화 공정 이전에 실행함으로서 실리사이드에 가해지는 열적 결함을 제거할 수가 있으며, 종래의 폴리사이드 게이트를 식각할 때 발생되는 폴리실리콘 잔류물 및 반도체기판의 피팅문제와 폴리실리콘의 사다리꼴 모양의 포지티브경사 윤곽을 크게 개선시킬 수가 있다.Therefore, according to the method of the present invention described above, a high temperature thermal oxidation process such as the oxidation process of the gate oxide film 21 and the polysilicon 22 and the deposition oxide 20 is performed prior to the titanium disilation process to be applied to the silicide. Thermal defects can be eliminated and the polysilicon residues and semiconductor substrate fitting problems and polysilicon trapezoidal positive slope contours generated when etching conventional polyside gates can be greatly improved.
본 발명은 상기 실시예에 한정되지 않으며 수많은 변형이 본 발명의 기술적 사상 내에서 당 분야에 통상의 지식을 가진 자에 의해 실시 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that numerous modifications can be made by those skilled in the art within the technical idea of the present invention.
Claims (12)
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