KR940007659B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR940007659B1 KR940007659B1 KR1019910024667A KR910024667A KR940007659B1 KR 940007659 B1 KR940007659 B1 KR 940007659B1 KR 1019910024667 A KR1019910024667 A KR 1019910024667A KR 910024667 A KR910024667 A KR 910024667A KR 940007659 B1 KR940007659 B1 KR 940007659B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- polysilicon
- kpa
- semiconductor device
- oxide film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 49
- 229920005591 polysilicon Polymers 0.000 claims abstract description 49
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008018 melting Effects 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 2
- 239000003870 refractory metal Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
제1a도 내지 제1g도는 종래의 SAG(Self aligned gate) 형성방법을 공정순서에 따라 도시한 단면도.1A to 1G are cross-sectional views illustrating a conventional method for forming a self aligned gate (SAG) according to a process sequence.
제2a도 내지 제2f도는 본 발명에 의한 SAG형성방법을 공정순서에 따라 도시한 단면도.2A to 2F are cross-sectional views showing the SAG forming method according to the present invention in the order of process.
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 폴리실리콘 게이트를 선택적으로 실리사이드화시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for selectively silicidating a polysilicon gate.
최근, 반도체 메모리장치의 초고집적화로 인해 배선의 폭은 좁아지고 길이는 더 길어짐에 따라 배선저항이 더욱 증가되므로 연결배선으로서 불순물이 확산된 단결정실리콘이나 고농도의 폴리실리콘을 사용하는데는 큰 제약이 따르고 있다.In recent years, due to the ultra-high integration of semiconductor memory devices, the wiring width is further increased as the width of the wiring becomes narrower and the length becomes longer. Therefore, there is a big limitation in using single crystal silicon or polysilicon with high concentration of impurities as connection wiring. have.
따라서 상기 문제에 대한 해결책으로 폴리실리콘 게이트물질을 대체하거나 보충할 만한 고전도도의 물질의 개발이 요구되었다.Therefore, the development of a high-conductivity material that can replace or supplement the polysilicon gate material as a solution to the problem.
이러한 목적에 사용하기 위한 고전도도의 물질로 MoSi2, WSi2,TaSi2및 TiSi2등과 같은 고융점금속실리사이드(Refractory metal silicide)가 폴리실리콘 게이트의 대체물질로 이용되고 있다.Highly conductive materials such as MoSi 2 , WSi 2 , TaSi 2 , TiSi 2, and the like are used as substitutes for polysilicon gates.
상기 고융점금속실리사이드를 폴리실리콘게이트에 이용한 폴리사이드(Polycide)구조가 초고집적 반도체장치에 광범위하게 사용되고 있다. 폴리사이드공정은 실질적으로 폴리실리콘게이트공정과 동일하게 진행되는데, 게이트산화막형성 및 채널이온주입까지는 동일하고 그후 폴리실리콘을 증착하는 대신 폴리실리콘과 실리사이드층을 연속적으로 증착한 후 실리사이드를 균질화시키기 위해 고온처리를 행한 다음 상기 폴리실리콘과 실리사이드의 혼합층을 건식식각에 의해 게이트 패턴으로 패터닝하게 된다. 그러나 상기와 같은 종래의 게이트 폴리실리콘에 고융점금속을 증착한 후 열처리하여 실리사이드화(Silicidation)시킨 후 패터닝하는 방법은 다음과 같은 문제점이 있었다.Background Art A polycide structure using the high melting point metal silicide as a polysilicon gate has been widely used in an ultra high density semiconductor device. The polyside process is substantially the same as the polysilicon gate process, and the gate oxide film formation and the channel ion implantation are the same, and then the polysilicon and the silicide layer are continuously deposited instead of the polysilicon, followed by the high temperature to homogenize the silicide. After the treatment, the mixed layer of polysilicon and silicide is patterned into a gate pattern by dry etching. However, the conventional method of depositing a high melting point metal on the gate polysilicon as described above, followed by heat treatment, silicidation, and patterning has the following problems.
즉, 고융점금속실리사이드 식각시 폴리머(Polymer)가 형성되어 폴리실리콘게이트가 정의 경사(Positive Slope)의 프로파일을 가지며, 게이트산화막의 두께가 110Å이하로 얇을 경우에는 액티브영역에 피팅(Pitting)이 생긴다. 또한 폴리실리콘 식각시에 손상된 게이트 산화막의 엣지(Edge)부위를 보상해 주기 위해 진행되는 게이트폴리 실리콘산화공정과 같은 고온에서 행해지는 공정들이 실리사이드화공정 다음에 진행됨에 따라 형성된 실리사이드가 쉽게 열화되는 문제점이 있었다.That is, a polymer is formed during the etching of the high melting point metal silicide, so that the polysilicon gate has a positive slope profile, and when the gate oxide film is thinner than 110Å, a fitting occurs in the active region. . In addition, the silicide formed easily deteriorates as the processes performed at a high temperature such as the gate polysilicon oxidation process, which is performed to compensate for the edge portion of the damaged gate oxide film during polysilicon etching, are performed after the silicide process. There was this.
상기의 문제점을 해결하기 위한 방법으로서 폴리실리콘위에 증착된 SiN을 이용하여 게이트폴리실리콘 윗부분만 실리사이드화시키는 셀프얼라인게이트(Self Aligned Gate : 이하 SAG라 한다) 공정이 제안되었다. 제1a도 내지 제1g도를 참조하여 이를 설명하면 다음과 같다.As a method for solving the above problems, a self-aligned gate (SAG) process is proposed in which a top portion of the gate polysilicon is silicided using SiN deposited on polysilicon. Referring to Figures 1a to 1g it will be described as follows.
반도체 기판(1)상에 게이트산화막(2)을 침적하고 이 게이트산화막(2)위에 폴리실리콘(3)과 SiN(4)을 차례로 침적한 후(제1a도), 게이트 패턴으로 패터닝하고(제1b도) 제 1 차 게이트폴리실리콘사화(Gate Polysilicon oxidation-1 ; GPox-1) 공정을 행하여 소오스/드레인영역상에 산화막을 형성하고 이 산화막을 통한 이온주입을 실시하여 n-영역(11)을 형성한 다음, 게이트 측면에 산화막스페이서(5)를 형성한다)제1c도).After depositing the gate oxide film 2 on the semiconductor substrate 1 and depositing the polysilicon 3 and SiN (4) sequentially on the gate oxide film (2) (Fig. 1a), and patterned in a gate pattern 1b) A first gate polysilicon oxidation-1 (GPox-1) process is performed to form an oxide film on a source / drain region, and ion implantation through the oxide film is performed to form the n-region 11. After the formation, an oxide film spacer 5 is formed on the side of the gate (Fig. 1C).
이어서 제 2 차 게이트 폴리실리콘산화(Gate Polysilicon oxidation-2 ; GPox-2)공정을 행하여 소오스/드레인 영역상에 산화막(6)을 형성하고 이 산화막(6)을 통한 이온 주입을 실시하여 n+영역(12)을 형성한다(제1d도). 다음 상기 폴리실리콘게이트(3)상의 SiN을 인산에서 제거(Strip)한 다음(제1e도), 고융점금속 예컨대 Ti(9)를 침적하고 나서(제1f도) 열처리 공정과 선택식각을 통해 상기 폴리실리콘게이트(3)위에만 국부적으로 Ti-실리사이드(10)를 형성시킨다(제1g도).Subsequently, a second gate polysilicon oxidation-2 (GPox-2) process is performed to form an oxide film 6 on the source / drain regions, and ion implantation through the oxide film 6 is performed to perform n + region ( 12) (FIG. 1d). Next, SiN on the polysilicon gate 3 is stripped from phosphoric acid (FIG. 1e), and then a high melting point metal such as Ti (9) is deposited (FIG. 1f), followed by heat treatment and selective etching. Ti-silicide 10 is locally formed only on the polysilicon gate 3 (FIG. 1g).
그러나 상기 종래의 SAG공정에 있어서는 GPox-2 공정시 게이트 폴리실리콘이 제1d도에 도시된 바와 같이 산화되어 채널 길이가 짧아지게 되고, 또한 SiN제거공정시에 제1e도에 도시된 바와같이 폴리실리콘(3)이 손상을 입어 Ti-실리사이드의 저항이 증가하는 문제점이 있다.However, in the conventional SAG process, the gate polysilicon is oxidized in the GPox-2 process as shown in FIG. 1d to shorten the channel length, and the polysilicon as shown in FIG. 1e in the SiN removal process. (3) There is a problem that the damage of Ti-silicide increases due to this damage.
따라서 본 발명은 상술한 문제점을 해결하기 위하여 SAG공정시의 폴리실리콘게이트의 산화를 방지함과 동시에 폴리실리콘게이트에 가해시는 손상을 방지할 수 있는 SAG형성방법을 제공하는 것을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a SAG formation method capable of preventing the damage to the polysilicon gate at the same time to prevent the oxidation of the polysilicon gate during the SAG process in order to solve the above problems.
상기 목적을 달성하기 위해 본 발명의 방법은 반도체장치의 폴리사이게이트전극의 형성방법에 있어서, 반도체기판상에 게이트 산화막, 폴리실리콘층, 얇은 산화막 및 질화막을 순차적층한 후 게이트 전극패턴으로 패터닝하는 공정과 ; 결과물전면에 얇은 질화막과 스페이서 산화막을 침적하고 에치백하여 게이트전극측면에 스페이서를 형성하는 공정; 게이트폴리실리콘산화를 행한 후 이온 주입하여 소오스/드레인 영역을 형성하는 공정; 상기 폴리실리콘층상의 상기 얇은 산화막과 질화막을 제거하는 공정; 결과물 전면에 고융점금속을 침적하는 공정; 및 열처리공정과 선택식각방법에 의해 상기 폴리실리콘층에만 상기 고융점 금속실리사이드를 형성시키는 공정을 구비한 것을 특징으로 한다.In order to achieve the above object, the method of the present invention is a method of forming a polysigate electrode of a semiconductor device, comprising sequentially forming a gate oxide film, a polysilicon layer, a thin oxide film and a nitride film on a semiconductor substrate and then patterning the gate electrode pattern. Process; Depositing and etching back a thin nitride film and a spacer oxide film on the entire surface of the resultant to form a spacer on the gate electrode side; Performing gate polysilicon oxidation followed by ion implantation to form source / drain regions; Removing the thin oxide film and the nitride film on the polysilicon layer; Depositing a high melting point metal on the entire surface of the resultant; And forming the high melting point metal silicide only in the polysilicon layer by a heat treatment process and a selective etching method.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2f도에 본 발명에 의한 SAG형성방법을 공정순서에 따라 도시하였다.2A to 2F show the SAG formation method according to the present invention in the order of the process.
제2a도를 참조하면, 반도체기판(1)위에 게이트산화막(2), 폴리실리콘(3)을 차례로 침적하고 80Å~120Å, 바람직하게는 100Å의 얇은 산화막(7)을 상기 폴리실리콘(3)상에 침적한 후 이어서 100Å~500Å정도의 산화막(4)을 형성시킨다.Referring to FIG. 2A, a gate oxide film 2 and a polysilicon 3 are deposited on the semiconductor substrate 1 in sequence, and a thin oxide film 7 of 80 kPa to 120 kPa, preferably 100 kPa is deposited on the polysilicon 3. After immersion in, an oxide film 4 of about 100 kV to 500 kV is formed.
제2b도를 참조하면, 상기 공정후 사진식각공정에 의해 게이트 패턴으로 패터닝하고 GPox-1 공정을 행하여 소오스/드레인 영역상에 산화막을 형성한 후 이 산화막을 통하여 불순물을 이온 주입하여 N-영역(11)을 형성한 다음 100Å이하의 얇은 질화막(8)과 1000Å~2000Å 두께의 스페이서산화막(5)을 상기 결과물전면에 차례로 형성한다.Referring to FIG. 2B, an oxide film is formed on a source / drain region by patterning a gate pattern by a photolithography process after the process and performing a GPox-1 process, and then ion implanted impurities through the oxide film to form an N-region ( 11), a thin nitride film 8 having a thickness of 100 kPa or less and a spacer oxide film 5 having a thickness of 1000 k?
제2c도를 참조하면, 상기 스페이서산화막(5)을 에치백하여 게이트 측면에 스페이서를 형성한다. 이때, 스페이서 아래 부분의 얇은 질화막(8)만 남고 나머지 부분의 얇은 질화막은 모두 제거된다.Referring to FIG. 2C, the spacer oxide layer 5 is etched back to form a spacer on the side of the gate. At this time, only the thin nitride film 8 in the lower part of the spacer remains and the thin nitride film in the remaining part is removed.
제2d도를 참조하면, GPox-2 공정에 의해 500Å 정도의 게이트 폴리실리콘산화막(6)을 소오스/드레인영역상에 형성한 다음 이온 주입 공정을 행하여 N+영역(12)을 형성하여 LDD구조의 소오스/드레인 영역을 완성시킨다.Referring to FIG. 2D, a gate polysilicon oxide film 6 of about 500 kV is formed on a source / drain region by a GPox-2 process, followed by an ion implantation process to form an N + region 12 to form an LDD structure. Complete the source / drain area.
제2e도를 참조하면, 인산용액으로 상기 폴리실리콘게이트(3)위의 질화막을 제거하고 이어서 100 : 1로 순수에 희석된 HF로 상기 얇은 산화막을 제거한 다음 Ti(9)를 상기 결과물 전면에 500Å~700Å 두께로 침적시킨다.Referring to FIG. 2E, the nitride film on the polysilicon gate 3 is removed with a phosphoric acid solution, and then the thin oxide film is removed with HF diluted in 100: 1 pure water, and then Ti (9) is applied to the entire surface of the product. Dip to ~ 700mm thick.
제2f도를 참조하면, 상기 침적시킨 Ti(9)를 RTP(Rapid Thermal Process)를 이용하여 N2분위기에서 20초~40초, 바람직하게는 30초간 630℃~675℃의 온도로 1차 어닐링을 행한 후 H2SO4: H2O2=3 : 1의 식각액을 이용한 선택식각방법으로 반응하지 않은 Ti를 제거한 다음 다시 RTP를 이용하여 N2분위기에 20초~40초, 바람직하게는 30초간 750℃~950℃, 바람직하게는 850℃의 온도로 2차 어닐링을 행하여 폴리실리콘게이트(3) 윗부분만 국부적으로 실리사이드화(10)시킨다.Referring to FIG. 2f, the deposited Ti (9) is first annealed at a temperature of 630 ° C. to 675 ° C. for 20 seconds to 40 seconds, preferably 30 seconds in an N 2 atmosphere using a rapid thermal process (RTP). After the reaction, the unreacted Ti was removed by a selective etching method using an etchant of H 2 SO 4 : H 2 O 2 = 3: 1, and then 20 seconds to 40 seconds, preferably 30, in an N 2 atmosphere using RTP. Second annealing is carried out at a temperature of 750 ° C. to 950 ° C., preferably 850 ° C. for a second, so that only the upper portion of the polysilicon gate 3 is silicided 10.
이상 상술한 바와같이 본 발명에 의하면, GPox-1 공정 및 GPox-2 공정과 같은 고온에서 행하는 공정을 Ti-실리사이드형성전에 실시함으로써 Ti-실리사이드에 가해지는 열적스트레스를 감소시킬 수 있으며, 특히 SAG 공정에 있어서 GPox-2 공정시에 게이트폴리실리콘이 산화되어 채널길이가 짧아지는 것과 게이트폴리실리콘위의질화막제거시에 폴리실리콘이 손상되는 것을 방지할 수 있으므로 반도체장치의 신뢰성 향상에 기여할 수 있게 된다.As described above, according to the present invention, the thermal stress applied to the Ti-silicide can be reduced by performing a process performed at a high temperature such as the GPox-1 process and the GPox-2 process before the Ti-silicide formation, and in particular, the SAG process. In the GPox-2 process, the gate polysilicon is oxidized to shorten the channel length and damage to the polysilicon upon removal of the nitride film on the gate polysilicon can contribute to improving the reliability of the semiconductor device.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024667A KR940007659B1 (en) | 1991-12-27 | 1991-12-27 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024667A KR940007659B1 (en) | 1991-12-27 | 1991-12-27 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930015065A KR930015065A (en) | 1993-07-23 |
| KR940007659B1 true KR940007659B1 (en) | 1994-08-22 |
Family
ID=19326271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910024667A KR940007659B1 (en) | 1991-12-27 | 1991-12-27 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940007659B1 (en) |
-
1991
- 1991-12-27 KR KR1019910024667A patent/KR940007659B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930015065A (en) | 1993-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2857006B2 (en) | Self-aligned cobalt silicide on MOS integrated circuits. | |
| US4786609A (en) | Method of fabricating field-effect transistor utilizing improved gate sidewall spacers | |
| KR100190757B1 (en) | Method of forming mosfet | |
| US20050130380A1 (en) | Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level | |
| US5266156A (en) | Methods of forming a local interconnect and a high resistor polysilicon load by reacting cobalt with polysilicon | |
| US4445266A (en) | MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance | |
| JP2874626B2 (en) | Method for manufacturing semiconductor device | |
| US6303494B1 (en) | Method of forming gate electrode in semiconductor device | |
| KR940007659B1 (en) | Manufacturing method of semiconductor device | |
| KR100223736B1 (en) | Method of manufacturing semiconductor device | |
| US4216573A (en) | Three mask process for making field effect transistors | |
| US6316804B1 (en) | Oxygen implant self-aligned, floating gate and isolation structure | |
| KR100313089B1 (en) | Method for manufacturing semiconductor device | |
| US6221745B1 (en) | High selectivity mask oxide etching to suppress silicon pits | |
| JPH05291180A (en) | Manufacture of semiconductor integrated | |
| KR19980060621A (en) | Manufacturing method of semiconductor device | |
| JP2819918B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| KR950000153B1 (en) | Manufacturing method of semiconductor device | |
| KR100255008B1 (en) | Manufacture method of semiconductor apparatus | |
| KR0172263B1 (en) | Method of manufacturing semiconductor device | |
| KR940007664B1 (en) | Forming method of saliside of semiconductor device | |
| KR100431311B1 (en) | Method of manufacturing semiconductor device for preventing loss of impurities and degradation of gate | |
| KR19980055970A (en) | Transistor manufacturing method | |
| KR930009479B1 (en) | Manufacturing method of insulated gate type fet | |
| KR20000004531A (en) | Method for manufacturing a gate insulator of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20060728 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |