KR940022762A - Bump Formation Method of Semiconductor Device - Google Patents

Bump Formation Method of Semiconductor Device Download PDF

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Publication number
KR940022762A
KR940022762A KR1019930004090A KR930004090A KR940022762A KR 940022762 A KR940022762 A KR 940022762A KR 1019930004090 A KR1019930004090 A KR 1019930004090A KR 930004090 A KR930004090 A KR 930004090A KR 940022762 A KR940022762 A KR 940022762A
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KR
South Korea
Prior art keywords
layer
seed metal
bump
semiconductor device
metal layer
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Application number
KR1019930004090A
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Korean (ko)
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KR960004093B1 (en
Inventor
백영상
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문정환
금성일렉트론 주식회사
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Priority to KR1019930004090A priority Critical patent/KR960004093B1/en
Publication of KR940022762A publication Critical patent/KR940022762A/en
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Publication of KR960004093B1 publication Critical patent/KR960004093B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체소자의 범프형성방법에 관한 것으로, 공정의 간소화 및 공정시간 단축을 도모하기 위하여 반도체소자의 각 본드 패드(1)위에 범프를 형성하는 방법에 있어서, 반도체소자(3)의 상면에 피알을 코칭하여 소정높이의 제1피알층(11)을 형성한후 t자의 각 본드 패드(1) 부분을 오픈하는 단계와, 상기 제1피알층(11)의 상면에 캐소드메탈을 디포지션하여 시드메탈층(4)을 형성하는 단계와, 상기 시드메탈층(4)의 상면에 재차 피알을 라미네이션하여 소정높이의 제2피알층(12)을 형성한후 범프형성 에리어(12a)를 오픈하는 단계와, 상기 범프형성 에리어(12a)에 범프메탈을 일렉트로 플래팅 방식으로 디포지션하여 범프(13)를 형성하는 단계와, 상기 제2피알층(12) 제거단계 및 반도체소자를 가열하고 클링함으로써 열팽창계수 차이에 의해 시드메탈층(4)과 제1피알층(11)이 서로 분리되게 한후 울트라 소닉등 기계적인 충격을 가하여 여분의 시드메탈층(4)과 제1피알층(11)을 동시에 제거하는 단계로 구성한 것이다. 따라서 여분의 시드메탈층이 기계적인 충격에 의해 제거되므로 공정이 보다 간소해질뿐만 아니라 시드메탈층의 재질을 보다 폭넓게 선택할 수 있게 되고, 공정시간이 단축되는 등의 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump forming method of a semiconductor device. In order to simplify the process and shorten the process time, a bump is formed on each bond pad 1 of the semiconductor device. Coaching the PAL to form the first PAL layer 11 having a predetermined height, and then opening each of the t-shaped bond pads 1, and depositing a cathode metal on the upper surface of the first PAL layer 11. Forming a seed metal layer (4), laminating the pellet again on the top surface of the seed metal layer (4) to form a second pellet layer 12 of a predetermined height and then opening the bump forming area (12a) Forming a bump 13 by depositing the bump metal on the bump forming area 12a by an electroplating method, removing the second film layer 12, and heating and kneading the semiconductor device. Seed metal layer 4 and the seed metal layer due to the difference in thermal expansion coefficient The first PAL layer 11 is separated from each other and then subjected to mechanical shock such as ultra sonic to remove the extra seed metal layer 4 and the first PAL layer 11 simultaneously. Therefore, since the extra seed metal layer is removed by a mechanical impact, not only the process is simpler but also the material of the seed metal layer can be selected more widely, and the process time is shortened.

Description

반도체소자의 범프형성방법Bump Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도의 (가)(나)(다)(라)(마)(바)는 본 발명에 의한 반도체소자의 범프형성방법을 보인 공정도.(A), (b), (d), (e) and (b) of FIG.

Claims (3)

반도체소자의 각 본드 패드(1)위에 범프를 형성하는 방법이 있어서, 반도체소자(3)의 상면에 피알을 코팅하여 소정높이의 제1피알층(11)을 형성한후 소자의 각 본드 패드(1) 부분을 오픈하는 단계와, 상기 제1피알층(11)의 상면에 캐소드메탈을 디포지션하여 시드메탈층(4)을 형성하는 단계와, 상기 시드메탈층(4)의 상면에 재차 피알을 라미네이션하여 소정높이의 제2피알층(12)을 형성한후 범프형성 에리어(12a)를 오픈하는 단계와, 상기 범프형성 에리어(12a)에 범프메탈을 일렉트로 플래팅 방식으로 디포지션하여 범프(13)를 형성하는 단계와, 상기 제2피알층(12) 제거단계 및 반도체소자를 가열하고 클링함으로써 열팽창계수 차이에 의해 시드메탈층(4)과 제1피알층(11)이 서로 분리되게 한후 울트라 소닉등 기계적인 충격을 가하여 여분의 시드메탈층(4)과 제1피알층(11)을 동시에 제거하는 단계로 이루어지는 반도체소자의 범프형성방법.In the method of forming bumps on the bond pads 1 of the semiconductor device, the first film layer 11 having a predetermined height is formed by coating a film on the upper surface of the semiconductor device 3, and then each bond pad of the device ( 1) opening a portion, depositing a cathode metal on the top surface of the first PAL layer 11 to form a seed metal layer 4, and again forming a seed metal layer on the top surface of the seed metal layer 4 Laminating a second PAL layer 12 having a predetermined height, and then opening the bump forming area 12a, and depositing a bump metal on the bump forming area 12a by electroplating. 13) and the seed metal layer 4 and the first PAL layer 11 are separated from each other by the thermal expansion coefficient difference by the step of removing the second PAL layer 12 and the heating and kneading of the semiconductor device. Extra seed metal layer (4) and first skin by applying mechanical shock such as ultra sonic A bump forming method for a semiconductor device comprising the step of simultaneously removing the egg layer (11). 제1항에 있어서, 상기 제1피알층(11)의 패드부분 오픈 공정시 그 형상이 외향만곡형으로 완만하게 경사지도록하여 그 위에 디포지션되는 시드메탈층(4)이 반도체소자상에서 오픈되는 부분이 없도록 하는 것을 특징으로 하는 반도체소자의 범프형성방법.The part of claim 1, wherein the seed metal layer 4 is formed on the semiconductor device so that the shape of the pad portion of the first PAL layer 11 is gradually inclined to the outwardly curved shape and is deposited thereon. The bump forming method of a semiconductor device, characterized in that there is no. 제1항에 있어서, 상기 제2피알층(12)의 높이를 파인피치에서도 범프형성을 용이하게 하기 위하여 범프의 높이보다 높게 라미네이션하는 것을 특징으로 하는 반도체소자의 범프형성방법.The method of claim 1, wherein the height of the second PAL layer is greater than the height of the bump to facilitate bump formation even at the fine pitch. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930004090A 1993-03-17 1993-03-17 Manufacturing method of bump of semiconductor device KR960004093B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930004090A KR960004093B1 (en) 1993-03-17 1993-03-17 Manufacturing method of bump of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019930004090A KR960004093B1 (en) 1993-03-17 1993-03-17 Manufacturing method of bump of semiconductor device

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KR940022762A true KR940022762A (en) 1994-10-21
KR960004093B1 KR960004093B1 (en) 1996-03-26

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403691B1 (en) * 1995-03-09 2004-01-07 소니 가부시끼 가이샤 Semiconductor device and its manufacture
KR100450243B1 (en) * 2002-04-09 2004-09-24 아남반도체 주식회사 A manufacturing method of bump for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403691B1 (en) * 1995-03-09 2004-01-07 소니 가부시끼 가이샤 Semiconductor device and its manufacture
KR100450243B1 (en) * 2002-04-09 2004-09-24 아남반도체 주식회사 A manufacturing method of bump for semiconductor device

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Publication number Publication date
KR960004093B1 (en) 1996-03-26

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