KR940022703A - Wiring Manufacturing Method of Semiconductor Device - Google Patents

Wiring Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940022703A
KR940022703A KR1019930004557A KR930004557A KR940022703A KR 940022703 A KR940022703 A KR 940022703A KR 1019930004557 A KR1019930004557 A KR 1019930004557A KR 930004557 A KR930004557 A KR 930004557A KR 940022703 A KR940022703 A KR 940022703A
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KR
South Korea
Prior art keywords
insulating layer
contact
layer
mask
upper wiring
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Application number
KR1019930004557A
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Korean (ko)
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KR960006703B1 (en
Inventor
박해성
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019930004557A priority Critical patent/KR960006703B1/en
Publication of KR940022703A publication Critical patent/KR940022703A/en
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Publication of KR960006703B1 publication Critical patent/KR960006703B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

본 발명은 고립적 반도체 소자의 배선 제조방법에 관한 것으로, 하부도전층 상부에 제1절연층, 제2절연층, 제3절연층을 적층하고 콘택마스크를 이용하여 콘택영역의 제3절연층, 제2절연층, 제1절연층을 식각하여 다수의 콘택홀을 형성하는 공정과, 콘택패드용 도전층을 증착하고, 콘택패드 마스크를 이용한 패턴공정으로 다수의 콘택패드를 형성하는 공정과, 예정된 콘택패드에서 이웃하는 콘택패드의 일정부분까지 노출되는 상부배선 마스크를 이용하여 노출된 제3절연층 및 제2절연층을 순차적으로 건식식각한 다음, 제2절연층을 베리어층으로 한 습식식각 공정으로 제3절연층을 제거하여 제2절연층 가장자리에 언더컷팅이 발생되도록 하는 공정과, 상기 상부배선용 도전층을 전체구조 상부에 증착하고 마스크없이 건식식각하여 제3절연층 하부의 언더컷팅된 부분을 따라 상부배선용 도전층을 남긴 상부배선을 형성하는 공정으로 포함하는 기술이다.The present invention relates to a method for manufacturing a wiring of an isolated semiconductor device, wherein the first insulating layer, the second insulating layer, and the third insulating layer are stacked on the lower conductive layer, and the third insulating layer and the first insulating layer of the contact region are formed using a contact mask. 2) forming a plurality of contact holes by etching the insulating layer and the first insulating layer, depositing a conductive layer for contact pads, forming a plurality of contact pads in a pattern process using a contact pad mask, and a predetermined contact The exposed third insulating layer and the second insulating layer are sequentially dry-etched using the upper wiring mask exposed to a portion of the neighboring contact pads from the pad, and then wet etching using the second insulating layer as a barrier layer. Removing the third insulating layer so that undercutting occurs at the edge of the second insulating layer; depositing the upper conductive layer on the entire structure, and dry etching without a mask to freeze the lower portion of the third insulating layer. Along the cut portion of a technique comprising the step of forming the upper wiring leaving the upper wiring conductive layer.

Description

반도체 소자의 배선 제조방법Wiring Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 의해 하부도전층에 콘택되는 상부배선을 형성할 때 주요 마스크를 배열한 레이아웃도.4 is a layout diagram in which main masks are arranged when forming the upper wiring contacting the lower conductive layer according to the present invention.

제5a도 내지 제5g도는 본 발명에 의해 하부도전층에 콘택되는 콘택패드와 상부배선을 형성하는 공정을 제4도의 A-A선을 따라 도시한 단면도.5A to 5G are cross-sectional views taken along line A-A of FIG. 4 showing a process of forming a contact pad and an upper wiring contacted to the lower conductive layer according to the present invention.

제6a도 내지 제6g도는 본 발명에 의해 콘택영역이 아닌 곳에서 상부배선을 형성하는 공정을 제4도의 B-B선을 따라 도시한 단면도이다.6A to 6G are cross-sectional views showing the process of forming the upper wiring in a non-contact area according to the present invention along the line B-B in FIG.

Claims (4)

반도체소자 배선 제조방법에 있어서, 하부도전층 상부에 제1절연층, 제2절연층, 제3절연층을 적층하고 콘택마스크를 이용하여 콘택영역의 제3절연층, 제2절연층, 제1절연층을 식각하여 다수의 콘택홀을 형성하는 공정과, 콘택패드용 도전층을 증착하고, 콘택패드 마스크를 이용한 패턴공정으로 다수의 콘택홀에 매립된 콘택패드를 형성하는 공정과, 예정된 콘택패드에서 이웃하는 콘택패드의 일정부분까지 노출되는 상부배선 마스크를 이용하여 예정된 부분의 제3절연층 및 제2절연층을 순차적으로 건식식각한 다음, 제2절연층을 베리어층으로 한 습식식각 공정으로 제3절연층을 제거하여 제2절연층 가장자리에 언더컷팅이 발생되도록 하는 공정과, 상기 상부배선용 도전층을 전체구조 상부에 증착하고 마스크없이 건식식각하여 제3절연층 하부의 언더컷팅된 부분을 따라 상부배선용 도전층을 남긴 상부배선을 형성하는 공저을 포함하는 반도체 소자의 배선 제조방법.A method for manufacturing a semiconductor device wiring, comprising: laminating a first insulating layer, a second insulating layer, and a third insulating layer on an upper conductive layer, and using a contact mask to form a third insulating layer, a second insulating layer, and a first insulating layer. Etching the insulating layer to form a plurality of contact holes; depositing a contact layer conductive layer; forming a contact pad embedded in the plurality of contact holes by a pattern process using a contact pad mask; and a predetermined contact pad Sequentially dry-etch the third and second insulating layers of the predetermined portion using the upper wiring mask exposed to a predetermined portion of the neighboring contact pads, and then use a wet etching process using the second insulating layer as the barrier layer. Removing the third insulating layer so that undercutting occurs at the edge of the second insulating layer; depositing the upper wiring conductive layer on the entire structure, and dry etching without a mask to under under the third insulating layer. Gongjeoeul method of producing the wiring of a semiconductor device comprising forming an upper wiring leaving the upper wiring conductive layer along a portion tingdoen. 제1항에 있어서, 상기 제1절연층은 산화막으로, 제2절연층은 TEOS산화막으로, 제3절연층은 HTO산화막으로 각각 형성하는 것을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the first insulating layer is formed of an oxide film, the second insulating layer is formed of a TEOS oxide film, and the third insulating layer is formed of an HTO oxide film. 제1항에 있어서, 상기 콘택패드는 콘택홀에 각각 독립적으로 콘택되고, 콘택패드 상부면이 콘택홀보다 조금 크게 형성하는 것을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the contact pads are independently contacted to the contact holes, and the upper surface of the contact pads is slightly larger than the contact holes. 제1항에 있어서, 상기 상부배선은 콘택패드의 측면과 전기적으로 접속되어 형성되도록 제2절연층을 선택적으로 습식식각할 때 콘택패드의 측면이 노출되도록 하는 것을 특징으로 하는 반도체 소자의 배선 제조방법.The method of claim 1, wherein the upper wiring is exposed to the side surface of the contact pad when the second insulating layer is selectively wet-etched to be electrically connected to the side surface of the contact pad. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930004557A 1993-03-24 1993-03-24 Wire manufacturing method of semiconductor device KR960006703B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930004557A KR960006703B1 (en) 1993-03-24 1993-03-24 Wire manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930004557A KR960006703B1 (en) 1993-03-24 1993-03-24 Wire manufacturing method of semiconductor device

Publications (2)

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KR940022703A true KR940022703A (en) 1994-10-21
KR960006703B1 KR960006703B1 (en) 1996-05-22

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