KR940020683A

KR940020683A - Compressed Image Data Extension Circuit

Info

Publication number: KR940020683A
Application number: KR1019930002792A
Authority: KR
Inventors: 서윤석
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1993-02-26
Filing date: 1993-02-26
Publication date: 1994-09-16
Also published as: KR960003451B1

Abstract

본 발명은 압축된 영상데이타를 60Hz로 제어하고 신장된 영상데이타를 디스플레이 타이밍과 적절한 타이밍을 가지도록한 압축된 영상데이타 신장회로에 관한 것으로서, 이러한 본 발명의 목적은 클럭을 발생하는 클럭 발생부와, 데이타 압축/신장부에서 출력된 신호와 상기 클럭 발생부에서 얻어진 클럭을 래치시켜 출력하는 래치부와, 상기 데이타 압축/신장부 및 래치부에서 얻어진 신호를 동기화시켜 기록가능신호를 제어하는 기록신호 제어부와, D/A부에서 출력된 클럭에 따라 동기신호를 발생하는 동기신호 발생부와, 상기 동기신호 발생부로부터 얻어진 동기신호에 따라 판독 가능신호를 제어하는 판독신호제어부와, 상기 판독신호/기록신호 제어부의 출력을 인가 받아 상기 데이타 압축/신장부에서 출력된 데이타를 상기 D/A부에 인가하는 선입선출부를 구비함으로써 달성된다.The present invention relates to a compressed image data decompression circuit which controls the compressed image data at 60 Hz and has the extended image data having a display timing and an appropriate timing. The object of the present invention is to provide a clock generator for generating a clock; And a latch unit for latching and outputting a signal output from the data compression / extension unit and a clock obtained from the clock generator unit, and a write signal for controlling a recordable signal by synchronizing the signals obtained from the data compression / extension unit and the latch unit. A control unit, a synchronization signal generator for generating a synchronization signal according to the clock output from the D / A unit, a read signal controller for controlling a readable signal according to the synchronization signal obtained from the synchronization signal generator, and the read signal / First-in-first-out to receive the output of the recording signal control unit and apply the data output from the data compression / extension unit to the D / A unit. It is accomplished by comprising a.

Description

Compressed Image Data Extension Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명 압축된 영상데이타 신장회로 블럭구성도.1 is a block diagram of the compressed image data expansion circuit of the present invention.

제2도는 제1도의 기록 및 판독 제어타이밍도.2 is a write and read control timing diagram of FIG.

Claims

Data compression / extension means for compressing / extending the data obtained from the interface circuit, clock generation means for generating a clock of a constant period, and the signal output from the data compression / extension means is synchronized with a clock obtained from the clock generation means. Latch means for generating a control signal, write signal control means for controlling a recordable signal in accordance with signals obtained from the latch means and data compression / expansion means, and digital / analog for converting an input digital signal into an analog signal and outputting it; Conversion means, synchronization signal generation means for generating a synchronization signal in accordance with a clock output from the digital / analog conversion means, read signal control means for controlling a readable signal in accordance with the synchronization signal obtained from the synchronization signal generation means; A signal output from the read signal control means and the write signal control means Receiving the compressed image data expansion circuit, characterized in that said data compression / write and read data obtained by the decompression means, and a including a first-in-first-out means for applying the data of the record to the digital / analog conversion means.

※ Note: The disclosure is based on the initial application.