KR940017404A

KR940017404A - Data Retiming Circuit of Transmission System

Info

Publication number: KR940017404A
Application number: KR1019920024890A
Authority: KR
Inventors: 이재원
Original assignee: 정용문; 삼성전자 주식회사
Priority date: 1992-12-21
Filing date: 1992-12-21
Publication date: 1994-07-26
Also published as: KR960006466B1

Abstract

전송시스템의 데이타 리타이밍회로에서 저속의 데이타열을 고속의 리타이밍클럭에 의해 계속적으로 리타이밍함에 따라 데이타의 변화시점에서 에러가 발생하는 것을 개선한다.In the data retiming circuit of the transmission system, the slow data sequence is continuously retimed by the high speed retiming clock, thereby improving the error occurrence at the point of data change.

이를 위하여 상기 저속의 데이타열을 상기 리타이밍클럭에 동기하여 버퍼링하고, 상기 리타이밍클럭을 소정 분주 및 논리조합하여 상기 버퍼링된 데이타열의 각 데이타의 중간시점마다 상기 리타이밍클럭의 한주기동안 액티브되는 클럭인에이블신호를 발생하며, 상기 버퍼링된 데이타열의 각 데이타를 상기 클럭인에이블신호가 액티브될때마다 상기 리타이밍클럭에 의해 래치 출력한다.To this end, the low-speed data string is buffered in synchronization with the retiming clock, and the retiming clock is divided and logically combined to be activated for one period of the retiming clock at every intermediate point of the data of the buffered data string. A clock enable signal is generated, and each data of the buffered data string is latched by the retiming clock each time the clock enable signal is activated.

따라서 데이타가 안정된 시점에서 정확하게 리타이밍시켜 리타이밍시의 데이타 에러를 방지한다.Therefore, the data is retimed correctly at a stable point of time to prevent data errors during retiming.

Description

Data Retiming Circuit of Transmission System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 제1도의 각 부분의 동작파형도, 제3도는 본 발명에 따른 리타이밍회로도.2 is an operation waveform diagram of each part of FIG. 1, and FIG. 3 is a retiming circuit diagram according to the present invention.

Claims

A data retiming circuit of a transmission system for retiming and transmitting a low speed data sequence by a high speed retiming clock, comprising: buffer means for buffering the data sequence in synchronization with the retiming clock, and the retiming clock being predetermined; Retiming time control means for generating a clock enable signal that is activated during one period of the retiming clock by dividing and logically combining the data of the buffered data string with each clock in the buffered data string; And latch means for latching out by said retiming clock whenever an enable signal is activated.

2. The apparatus as claimed in claim 1, wherein the buffer means divides the retiming clock up to one-half frequency of the transmission clock into which the data sequence is input, and the second division means for dividing the transmission clock by two. And first and second latch circuits for alternately latching even-numbered data and odd-numbered data among the data of the data string each time the logical state of the two-division transfer clock changes. And selecting means for alternately selecting and outputting the data latched in the first and second latches each time the logic state of the retiming clock is changed.

A data retiming circuit of a transmission system for retiming and transmitting a low speed data string by a high speed retiming clock, comprising: first dividing means for dividing the retiming clock into two, four, and eight divisions; A second division means for dividing an input transmission clock by two divisions, and inverting the first transmission circuit; a first latch circuit for latching even-numbered data of each data in the data string by the second division transmission clock; and in each data of the data string. A second latch circuit for latching odd-numbered data by the inverted two-division transfer clock; and alternately latching the data latched in the first and second latches each time the logic state of the eight-division retiming clock changes. A logical combination of the selection means for outputting the selection and the two- and four-division retiming clocks, so that one of the retiming clocks is generated at each intermediate point of the data of the output data string of the selection means. A retiming clock control means for generating a clock enable signal that is activated during a period of time, and a third latch circuit for latching each data in the output data string of the selection means by the retiming clock whenever the clock enable signal is activated. A data retiming circuit of a transmission system, characterized in that consisting of.

4. The retiming clock control means according to claim 3, wherein the retiming clock control means inverts the quadrature retiming clock, the two-division retiming clock and the inverted four-division retiming clock, and outputs the clock enable signal. A data retiming circuit of a transmission system, comprising: an end gate.

※ Note: The disclosure is based on the initial application.