KR20090093510A - Semiconductor memory apparatus for high speed data input/output - Google Patents

Abstract

A semiconductor memory device for inputting/outputting high speed data is provided to arranged and output data corresponding to a system clock having a high frequency by securing a long operation margin for arranging data. A first serialization part(300A) serializes parallel inputted eight data, and outputs successive two data. A second serialization part(300B) receives an output of the first serialization part, and outputs successive two data. A third serialization part(300C) receives an output of the second serialization part, and outputs serialized eight data. Each data window of the successive two data outputted in the first serialization part is four times of each window of the serialized eight data. A phase moving part moves a phase of four data among the eight data as four times of each data window of the serialized eight data. A multiplexer multiplexes an output of the phase moving part and the other four data among the eight data, and outputs successive two data.

Description

Semiconductor memory device for high speed data input / output {SEMICONDUCTOR MEMORY APPARATUS FOR HIGH SPEED DATA INPUT / OUTPUT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of operating at high speed, and more particularly, to a data output control circuit and an operation method for sorting and controlling a plurality of data output from a semiconductor memory device operating at high speed.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device such as a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the data requesting device.

BACKGROUND OF THE INVENTION As the operating speed of a system composed of semiconductor devices becomes faster and technology related to semiconductor integrated circuits develops, semiconductor memory devices have been required to output or store data at a higher speed. In order for a semiconductor memory device to operate safely at a higher speed, several circuits in the semiconductor memory device must be able to operate at a high speed, and also a signal or data can be transferred at a high speed.

In order to speed up the operation of the semiconductor memory device, a plurality of internal operations that occur internally may be executed faster, or speeds of input / output of signals and data may be increased. In an example, a double data rate (DDR) semiconductor memory device outputs data in synchronization with a falling clock as well as a rising edge of a system clock in order to output data faster. Since two data can be input and output at one cycle of the system clock from one input / output stage of the semiconductor memory device, the input / output speed of the data is faster than that of the conventional semiconductor memory device. A semiconductor memory device capable of inputting and outputting four data has been proposed.

In order to output data at high speed, a prefetch operation has been used internally from a digital semiconductor memory device. Here, the prefetch operation refers to bringing the data or command to the storage means for operating at high speed before the data or command is processed. For example, a DDR semiconductor memory device (DDR SDRAM) employs an operation of accessing two bits of data from a memory cell and outputting the data pad to a data pad every one clock cycle. This operation is referred to as a two-bit prefetch operation. In addition, the digital2 semiconductor memory device (DDR2 SDRAM) employs a 4-bit prefetch operation, a method of accessing 4-bit data from a memory cell and outputting the data to a data pad every one clock cycle. Similarly, the DRAM3 semiconductor memory device (DDR3 SDRAM) employs an 8-bit prefetch operation that accesses 8-bit data from a memory cell and outputs it to a data pad every one clock cycle. As such, the semiconductor memory device had to increase data input / output speed in order to enable high-speed operation in response to a clock signal having a high frequency. As a result, each data input / output pad may be executed by a single read or write command. An operation method of reading or writing data corresponding to the minimum burst length (DQ) at one time is adopted. This method is called an N bits prefetch operation. N at this time is equal to the minimum burst length.

As described above, the recently proposed semiconductor memory device is required to input and output four data in one cycle of the system clock, and employs an 8-bit prefetch operation for high-speed input and output of such data. Eight data outputs corresponding to one read command from a unit cell are transferred in parallel through a corresponding sense amplifier and a data input / output line. In order to output the data transferred in parallel through one data pad, it must be serialized. To control this operation, the semiconductor memory device includes a plurality of data output circuits connected to each of the plurality of data input / output pads.

1 is a block diagram illustrating a data output circuit of a general semiconductor memory device.

As shown in the drawing, the data output circuit is configured to first pass four data D0, D2, D4, and D6 that are output from the unit cell and transferred in parallel in response to the selection signal SOSEB <2: 1>. Multiplexer 120, second multiplexer 140 for sequentially passing the other four data (D1, D3, D5, D7) output from the unit cell in parallel to the selection signal (SOSEB <2: 1>) ), A latch unit 160 for transmitting the four serialized data N2 transmitted from the second multiplexer 140 in response to the delay lock clock RCLK_DLL, and the first multiplexer 120 and the latch unit 160. The third multiplexer 180 is configured to sequentially transfer the data N1 and N3 transmitted from the N-M3 to the delay lock clock RCLK_DLL.

Referring to a specific operation, first, data to be transmitted in synchronization with the rising edge and the falling edge of the delay locked clock RCLK_DLL are separated and transferred to the first multiplexer 120 and the second multiplexer 140. Here, four data D0, D2, D4, and D6 transmitted to the first multiplexer 120 are output in synchronization with the rising edge of the delay locked clock RCLK_DLL and transmitted to the second multiplexer 140. The data D1, D3, D5, and D7 are output in synchronization with the falling edge of the delay locked clock RCLK_DLL.

Four data transmitted in parallel to the first and second multiplexers 120 and 140, respectively, are sequentially output and serialized one by one corresponding to the selection signal SOSEB <2: 1>. That is, four data inputted to the first multiplexer 120 are arranged and output in the order of D0, D2, D4, and D6, and data input to the second multiplexer 140 is the order of D1, D3, D5, and D7. The output is sorted as shown. Here, the selection signal SOSEB <2: 1> is a casing stored in a mode register set (MRS) based on specific address information (for example, A <2: 1>) input with a read command. It is generated corresponding to the delay time (CAS Latency, CL) and the burst type (burst type). That is, the activation time of the selection signal SOSEB <2: 1> is determined according to the cas delay time CL, and the start address is any one of 0 to 7 and the burst type is the sequential type and the interleaved method. The value is determined according to any of (Interleave Type). The data alignment shown in FIG. 1 assumes that all of the specific address information A <2: 1> and A <0> input corresponding to the read command are all zero.

The latch unit 160 receiving the four data N2 serialized through the second multiplexer 140 shifts the phase by 0.5 tCK (half period of the system clock) by using the delay locked clock RCLK_DLL. 3 is passed to the multiplexer 180. Finally, the third multiplexer 180 transfers the data N1 transferred from the first multiplexer 120 in response to the rising edge of the delay locked clock RCLK_DLL and corresponds to the falling edge of the delay locked clock RCLK_DLL. To transfer the data N3 transferred from the latch unit 160. As a result, the third multiplexer 180 generates data MXOUT in the order of D0, D1, D2, D3, D4, D5, D6, and D7 in response to the repeated rising edge and the falling edge of the delay locked clock RCLK_DLL. Is output.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1.

As shown, after the read command is input, data D0 to D7 are transmitted from a time point that is 0.5 tCK (half cycle of the external clock) before the CAS delay time (CL). Thereafter, the transmitted data D0 to D7 are serialized in response to the selection signal SOSEB <2: 1> and output from the cas delay time CL to the outside. Therefore, each of the first multiplexer 120 and the second multiplexer 140 in the data output circuit within 0.5 tCK must serialize four data input using the selection signal SOSEB <2: 1>.

As shown, sorting the data D0 output first among the plurality of data D0 to D7 has a lower operating margin than the time for sorting the data subsequently output. As described above, the data output circuit aligns data transmitted 0.5 tCK before being output to the outside using the selection signal SOSEB <2: 1> within 0.5 tCK. This operation is performed when the operating frequency is not high. It doesn't matter much. For example, when one cycle (1 tCK) of the system clock is 1 ns, the first multiplexer 120 and the second multiplexer 140 must serialize four data within 0.5 ns. However, the semiconductor memory device is required to operate in response to a system clock having a higher frequency, and the 4: 1 multiplexer (MUX) used as the first multiplexer 120 and the second multiplexer 140 shown in FIG. Given the operating margin of, it is difficult to serialize the data in less than 0.5 ns.

In addition, in the case of the data output circuit shown in FIG. 1, the data D0 to D7 at a time earlier than 0.5 tCK before being output to the outside (for example, 1 tCK or 2 tCK earlier than the cas delay time CL). When it is received, it is impossible to align and output the data D0 to D7 according to the cas delay time CL. Therefore, the semiconductor memory device using the data output circuit shown in FIG. 1 has a limit of an operating frequency, and such a structure cannot be applied to a semiconductor memory device operating at high speed.

The present invention is to improve the reliability of the operation by aligning the output data in the semiconductor memory device operating at a high speed, the system having a higher frequency by ensuring a longer operating margin for aligning the data transmitted therein Its characteristic is that data can be aligned and output in response to a clock.

The present invention provides a first serialization means for serializing eight data input in parallel to output four consecutive two data, and a second serial output means for receiving two outputs and outputting four consecutive data. A semiconductor memory device comprising a second serialization means and a third serialization means for receiving the output of the second serialization means and outputting eight serialized data.

In addition, the present invention provides a first serialization means for receiving four data input in parallel and outputting four consecutive two data having a data window four times as large as each window of the eight serialized data; Second serialization means for outputting two consecutive four data having a data window twice as large as each window of eight data serialized by receiving the output of the means, and serialized by receiving the output of the second serialization means A signal transmission device having third serialization means for outputting eight data is provided.

Furthermore, the present invention provides a first serialization step for outputting eight data transmitted from an internal unit cell corresponding to a read command in parallel to four consecutive two data, and two consecutive four data. A second serialization step for outputting four consecutive data is provided, and a third serialization step for outputting two consecutive four data as serialized eight data is provided.

A semiconductor memory device that is required to operate at a high speed should be able to input and output more data in a short time corresponding to a system clock. To this end, a semiconductor memory device according to an embodiment of the present invention outputs data corresponding to a read command. In order to output in parallel in time and output through the input / output pads at a time earlier than 1.5 tCK earlier than this point, sufficient operating margin for serialization is secured. In addition, the data output circuit in the semiconductor memory device has a plurality of multiplexers and a plurality of multiplexers for serializing the data input in parallel within an operating margin of 1.5 tCK and allowing the data to be output at a point after the cascade delay time after a read command is applied. A latch and a plurality of phase shifters are used to perform a stepwise serialization operation. The data output circuit of the present invention converts eight data inputted in parallel into four parallel data composed of two consecutive data first, and then converts the four parallel data into two parallel data composed of four consecutive data. Finally, two parallel data are converted into one serial data consisting of eight consecutive data. This ensures sufficient operating margin to align the data, which enables the semiconductor memory device to output aligned data in response to a system clock having a higher frequency.

According to the present invention, a data output circuit for serializing data output in parallel in a semiconductor memory device can sufficiently secure an operating margin for data alignment so that data corresponding to a read command corresponds to an external clock having a high frequency. There is an advantage that can be output to ensure a high speed operation of the semiconductor memory device.

Specifically, a semiconductor memory device using an embodiment of the present invention may perform a read operation corresponding to a high frequency clock of 5 Gbps or more, and in particular, when used in a semiconductor memory device for graphic data in which an operation speed is important, etc. Speed can be guaranteed to increase product competitiveness.

1 is a block diagram illustrating a data output circuit of a general semiconductor memory device.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1.

3 is a block diagram illustrating a data output circuit of a semiconductor memory device according to an embodiment of the present invention.

4 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 3.

FIG. 5 is a block diagram illustrating the serialization controller shown in FIG. 3.

FIG. 6 is a waveform diagram illustrating the operation of the serialization controller shown in FIG. 5.

FIG. 7 is a circuit diagram for describing the first phase shifter illustrated in FIG. 3.

FIG. 8 is a circuit diagram illustrating the first multiplexer shown in FIG. 3.

FIG. 9 is a circuit diagram for describing a fifth phase shifter illustrated in FIG. 3.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram illustrating a data output circuit of a semiconductor memory device according to an embodiment of the present invention.

As shown, the data output circuit receives the outputs of the first serializer 300A and the first serializer 300A for serializing eight data input in parallel to output four consecutive two data. A second serializer 300B for outputting two consecutive four data, and a third serializer 300C for outputting eight serialized data by receiving the output of the second serializer 300B. do.

Here, the first serialization unit 300A phases four data D4 to D7 of the eight data D0 to D7 by four times (4UI) of each data window UI of the eight serialized data. The first and second phase shifters 310A and 310B for moving, the other four data D0 to D3 among the eight data, and the outputs of the first and second phase shifters 310A and 310B are multiplexed to 4 First and second multiplexers 320A and 320B for outputting two consecutive data, and first and second latches 330A for latching outputs of the first and second multiplexers 320A and 320B. 330B).

In detail, odd-numbered data D0, D2, D4, and D6 of eight data D0 to D7 transmitted in parallel are serially paired and serialized by the first multiplexer 320A. To this end, the first phase shifter 310A first delays two data D4 and D6 among odd-numbered data by a window 4UI of data aligned by the first and second multiplexers 320A and 320B. Move it. Similarly, even-numbered data D1, D3, D5, and D7 are serialized and aligned using the second phase shifter 310B and the second multiplexer 320B. Four data paired by two data by the first and second multiplexers 320A and 320B are latched by the first and second latch units 330A and 330B, respectively. Here, each data window of four data including two consecutive data output from the first and second latch units 330A and 330B in the first serializer 300A is output from the third serializer 300C. 4 times each window of 8 serialized data.

In addition, the second serializer 300B, which receives four data output from the first and second latch units 330A and 330B, serializes two data D2-D6 and D3-D7 of the four data. Third and fourth phase shifters 340A and 340B for shifting the phase by two times (2UI) of each data window of eight data, and two other data among the four data (D0-D4 and D1-D5) And a third for outputting two consecutive four data (D0-D2-D4-D6, D1-D3-D5-D7) by multiplexing the outputs of the third and fourth phase shifters 340A and 340B. And fourth and fourth latch portions 360A and 360B for latching the outputs of the fourth multiplexers 350A and 350B and the third and fourth multiplexers 350A and 350B.

Specifically, the third and fourth phase shifters 340A and 340B may include two data D2 among the four data output from the first and second latch units 330A and 330B in the first serializer 300A. -D6, D3-D7) are delayed by using the divided clocks WCK / 2 and WCKB / 2 generated by dividing the data clocks WCK and WCKB at half frequency. Here, the data clocks WCK and WCKB are used as a reference for outputting the eight serialized data and have a frequency twice as high as that of the system clock. The newly proposed semiconductor memory device has a data clock WCK and WCKB. Output two data during one cycle of). That is, the data window UI of each of the eight serialized data corresponds to half of the period of the data clocks WCK and WCKB.

Each of the third and fourth phase shifters 340A and 340B uses two divided clocks WCK / 2 and WCKB / 2, each of which is four times the data window UI of each of the eight serialized data periods. (D2-D6, D3-D7) Delay each phase by twice the data window UI of each of the eight serialized data. Thereafter, each of the third and fourth multiplexers 350A and 350B is phased by the third and fourth phase shifters 340A and 340B among the four data output from the first and second latch units 330A and 330B. The two delayed data (D2-D6, D3-D7) are aligned with the other two data (D0-D4, D1-D5), respectively, so that two consecutive four data (D0-D2-D4-D6, D1-D3-D5-D7) is output. Finally, the third and fourth latch units 360A and 360B latch and output the outputs of the third and fourth multiplexers 350A and 350B to the third serializer 300C.

Finally, the third serialization unit 300C serializes one data D1-D3-D5-D7 of two consecutive four data D0-D2-D4-D6 and D1-D3-D5-D7. A fifth phase shifter 370 for shifting the phase by each data window UI of the eight data data and two consecutive four data (D0-D2-D4-D6, D1-D3-D5-D7) The serialized eight consecutive data (D0-D1-D2-D3-D4-D5-D6-D7) by multiplexing the outputs of the other one (D0-D2-D4-D6) and the fifth phase shifter 370. A fifth multiplexer 380 for outputting

Referring to FIG. 3, the data output circuit corresponds to a read data output signal RDOUTEN for activating data output in response to a read command and a divided clock WCK / 2 of the data clock WCK as a reference for the data output. A first control pulse POUT_CL15P for controlling the first and second phase shifters in the first serializer 300A, a second control pulse POUT_CL15 for controlling the first and second multiplexers 320A and 320B, And a serialization controller 390 for outputting a data transfer signal DOFFB for controlling the first and second latch units 330A and 330B.

4 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 3. In particular, the operation of the semiconductor memory device has been described with reference to the data clock WCK and the divided clock WCK / 2, and FIG. 4 shows that the frequency of the divided clock WCK / 2 is the same as that of the system clock. An example is a GDDR5 semiconductor memory device that outputs four data in one cycle tCK.

As shown in the drawing, the semiconductor memory device stores eight serialized data (D0-D1-D2-D3-D4-D5-D6-D7) serialized from the time after the cas delay time CL after the read command is applied. Output Specifically, in the semiconductor memory device, the read data output signal RDOUTEN corresponding to the read command is activated at a time point earlier than the cas delay time CL by 4tCK (4 periods of the system clock). Thereafter, the serialization controller 390 in the data output circuit generates a plurality of signals for controlling the first serializer 300A in response to the read data output signal RDOUTEN. In addition, the plurality of data D0 to D7 output from the internal unit cell is transferred to the data output circuit at a time point that is 2.5 tCK earlier than the cas delay time CL.

The plurality of data D0 to D7 are transferred to the data output circuit in parallel. The data output circuit serializes a plurality of data D0 to D7 input in parallel and outputs eight consecutive data D0-D1-D2-D3-D4-D5-D6-D7. First, the serialization control unit 390 activates the first control pulse POUT_CL15P at a time point that is 1.5 tCK earlier than the cas delay time CL in response to the read data output signal RDOUTEN. The first and second phase shifters 310A and 310B in the first serialization unit 300A correspond to the activated first control pulses POUT_CL15P and the four data D4 to D7 of the plurality of data D0 to D7. D7) delays the phase by 1tCK (4UI).

In addition, the serialization control unit 390 activates the second control pulse POUT_CL15 to a logic high level at a time point that is 1.5 tCK earlier than the cas delay time CL, such as the first control pulse POUT_CL15P. At this time, the inversion signal POUT_CL15B of the second control pulse POUT_CL15 is at a logic low level. In response to the inverted signal POUT_CL15B of the second control pulse POUT_CL15 and the second control pulse POUT_CL15, the first and second multiplexers 320A and 320B are connected to four pieces of data D0 to D3 input in parallel. The other four data D4 to D7 whose phases are shifted through the first and second phase shifters 310A and 310B are serialized. After four consecutive two data D0-D4, D2-D6, D1-D5, and D3-D7 are generated through the first and second multiplexers 320A and 320B, the first and second latch units ( The 330A and 330B transfer four pieces of data to the second serializer 300B in response to the data transfer signal DOFFB output from the serialization controller 390.

Of the four data transmitted to the second serializer 300B, two data D2-D6 and D3-D7 are input to the third and fourth phase shifters 340A and 340B and delayed by 0.5 tCK (2UI). do. Thereafter, the third and fourth multiplexers 350A and 350B are divided into four pieces of data, namely, two data delayed by the third and fourth phase shifters 340A and 340B, and the first and second latch units 330A and 330B. Receives 2 undelayed data output from) and serializes it into 2 data. The two serialized data are transferred to the third serializer 300C through the third and fourth latch units 360A and 360B, respectively. In particular, each of the third and fourth latch units 360A and 360B transfers data before 0.25 tCK of the cas delay time CL corresponding to the falling edge of the data clock WCK. 4, four data (D0-D4, D2-D6, D1-D5, D3-D7) transmitted to the input terminals (d0, d1, d2, d3) of the third and fourth multiplexers (350A, 350B) ) And the second serializer 300B through two data (D0-D2-D4-D6, D1-D3-D5-D7) at the output terminals d4 and d5 of the third and fourth multiplexers 350A and 350B. ) You can check the operation.

The data D1-D3-D5-D7 transmitted to the third serializer 300C through the fourth latch unit 360B is delayed in phase by the UI corresponding to the fifth phase shifter 370. The fifth multiplexer 380 through the third latch unit 360A is 0.25 tCK (half period of the data clock WCK) earlier than the cas delay time CL, that is, synchronized with the falling edge of the data clock WCK. When delivered to, one data D0-D2-D4-D6, rdo, which is delivered, starts to be output by the fifth multiplexer 380 in synchronization with the rising edge of the data clock WCK. On the other hand, after another data (D1-D3-D5-D7, fdo) delayed through the fifth phase shifter 370 is transferred to the fifth multiplexer 380 in synchronization with the rising edge of the data clock WCK. Output is started in synchronization with the falling edge of the data clock WCK by the fifth multiplexer 390. Through the above-described process, eight serialized data in which eight data D0 to D7, which have been transmitted in parallel since the cas delay time CL after the read command is applied, are serialized by the data output circuit and continuously output. Data is output as D0-D1-D2-D3-D4-D5-D6-D7.

FIG. 5 is a block diagram illustrating the serialization controller 390 shown in FIG. 3.

As shown, the serialization control unit 390 corresponds to the read data output signal RDOUTEN and the divided clock WCK / 2, and the first control pulse POUT_CL15P, the second control pulse POUT_CL15 and POUT_CL15B, and the data. A plurality of flip-flops 391, 392, 393 and first to third latches 396, 397, 398 for outputting a transmission signal are included. In particular, the first latch 396 outputs a first control pulse POUT_CL15P for controlling the first and second phase shifters 310A and 310B in response to the read data output signal RDOUTEN, and the second latch 396. 397 outputs second control pulses POUT_CL15 and POUT_CL15B having activation intervals of twice (1 tCK) in the period of the data clock WCK for controlling the first and second multiplexers 320A and 320B. . Finally, the data transfer signal DOFFB has an activation period of four times (2tCK) in the period of the data clock and is output through the third latch 398.

Specifically, if the read data output signal RDOUTEN is activated to a logic high level at a time point CL-4 that is four cycles earlier than the cas delay time CL after the read command is applied, a plurality of flip-flops are provided. 391, 392, and 393 phase shift the read data output signal RDOUTEN in response to the divided clock WCK / 2. The output terminal N2 of the second flip-flop 392 transitions to a logic high level at a time point CL-2 that is two cycles of the system clock earlier than the cas delay time CL. At this time, the AND gate 395 at the time inverted by the first inverter 399_1 of the divided clock WCK / 2 (that is, the falling edge of the divided clock WCK / 2) causes the AND gate 395 to generate a first control pulse POUT_CL15P. Activate. At this time, the first control pulse POUT_CL15P has an activation period for the period of the data clock WCK.

After the output terminal N2 of the second flip-flop 392 transitions to a logic high level, the first latch 396 generates a second control pulse POUT_CL15 in response to the falling edge of the divided clock WCK / 2. do. On the other hand, the second latch 397, which receives the output of the second inverter 399_2 inverting the output terminal N2 of the second flip-flop 392, corresponds to the falling edge of the divided clock WCK / 2. The inverted signal POUT_CL15B of the control pulse POUT_CL15 is generated. Here, the inverted signal POUT_CL15B of the second control pulse POUT_CL15 and the second control pulse POUT_CL15 may operate in response to the falling edge of the divided clock WCK / 2. Because of this, it may have an activation period of 1tCK (one cycle of the system clock).

In addition to activating the second control pulse POUT_CL15, the data transfer signal DOFFB is also generated by the third latch 398 that operates in response to the falling edge of the divided clock WCK / 2. However, the third latch 398 receives the outputs of the second and third flip-flops 392 and 393 through the OR gate 394, thereby transferring data having twice the activation period of the second control pulse POUT_CL15. Output of the signal DOFFB is possible.

6 is a waveform diagram illustrating the operation of the serialization control unit 390 shown in FIG. 5.

As illustrated, the serialization control unit 390 generates a plurality of signals based on the divided clock WCK / 2 in response to the read data output signal RDOUTEN. First, when the read data output signal RDOUTEN is activated, the phase is delayed by the period of the divided clock WCK / 2 through the plurality of flip-flops 391, 392, and 393. After the output terminal (N1, N2, N3) of 393), the first and second latches 396, 397 in the serialization control unit 390 correspond to the falling edge of the divided clock WCK / 2. 2 Generate the control pulses (POUT_CL15P, POUT_CL15, POUT_CL15B). In addition, the OR gate 394 performs an OR operation on the outputs of the second and third flip-flops 391 and 392 to output an output pulse having the double activation interval through the output terminal n4 to the third latch ( 398, the third latch 398 outputs the data transfer signal DOFFB in response to the falling edge of the divided clock WCK / 2.

FIG. 7 is a circuit diagram illustrating the first phase shifter 310A shown in FIG. 3.

As shown, the first phase shifting unit 310A includes a plurality of unit latches for phase shifting the plurality of data D4 and D6 respectively input in parallel, and the unit latch unit receives the input data d. Latch and invert the output of the third inverter 321 for inverting, the transfer gate 314 for delivering the output of the third inverter 321 in response to the first control pulse POUT_CL15P, and the transfer gate 314. Inverter latch 318 for outputting. In addition, the unit latch unit further includes a fourth inverter 316 for inverting the first control pulse POUT_CL15P to control the transfer gate 314. Although not shown, the second phase shifter 310B also includes the same components as the first phase shifter 310A.

FIG. 8 is a circuit diagram for describing the first latch unit 330A shown in FIG. 3.

As shown, the first latch unit 330A includes a plurality of unit latch units for latching a plurality of two consecutive data output from the first multiplexer 320A, and the unit latch unit includes a data transfer signal DOFFB. NAND gates 332 and NOR gates 332 for inverting and transferring each of the data in correspondence with each other are delivered at intervals of four times the respective data windows of the eight serialized data. And a inverter latch 336 for latching, inverting and outputting the output of the transfer gate 334.

Here, the negative logic gate 332 inverts the input data d to the transfer gate 334 when the data transfer signal DOFFB is at a logic high level, but the data transfer signal DOFFB is at a logic low level. In this case, the logic high level is transmitted to the transfer gate 334 regardless of the level of the input data d. In addition, the inverter latch 336 is also reset by the setting signal SETB. When the setting signal SETB is activated at a logic low level, the inverter latch 336 receives and outputs a logic low level value regardless of the output of the transmission gate 334.

FIG. 9 is a circuit diagram for describing the fifth phase shifter 370 illustrated in FIG. 3.

As illustrated, the fifth phase shifter 370 shifts the phase of the data d6 output from the fourth latch unit 360B in response to the data clock WCK, or during a test operation or a training operation. Outputs any data that is not synchronized with the system clock or data clock WCK.

Specifically, the fifth phase shifter 370 may include a data inversion unit 372 for inverting data in synchronization with the data clock WCK, and asynchronous data for outputting arbitrary data during a test operation or the training operation. A generator 374 and an inverter latch 376 for latching the output of the data inverting unit 372 and the asynchronous data generating unit 374 and outputting an inverted signal. The data inverting unit 372 inverts and transfers the data d6 input in synchronization with the rising edge of the data clock WCK, and the inverter latch 376 inverts the data transferred from the data inverting unit 372 to generate the first data inverted. Output to the multiplexer 380. The fifth multiplexer 380 receives data starting from the fifth phase shifter 370 in synchronization with the rising edge of the data clock WCK and outputs the data to the outside in response to the falling edge of the data clock WCK. .

On the other hand, in the case of a test operation or a training operation that does not output the data transmitted internally, the fifth phase shifter 370 may output arbitrary data by activating the asynchronous enable signal async_en and the asynchronous start signal async_do. Make sure At this time, the data clock WCK is deactivated to a logic low level.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes a first serialization step of outputting eight data, which are transmitted from an internal unit cell and input in parallel, as four consecutive two data in response to a read command. A second serialization step for outputting four consecutive two data as two consecutive four data, and a third serialization step for outputting two consecutive four data as eight serialized data; . Here, each data window of two consecutive data output in the first serialization step is four times each window of eight serialized data, and each data window of four consecutive data output in the second serialization step is serialized. It is twice the window of eight data.

Specifically, the first serializing step includes shifting phases of four data of eight data by four times each data window of the serialized eight data, and shifting the phase data of the other four data of eight data. Multiplexing four data to output four consecutive two data, and latching four consecutive two data.

Also, the second serialization step is for shifting the phase of two data out of four consecutive two data by twice the data window of the eight data serialized, and the other two out of four consecutive two data. Multiplexing data and phase shifted data to output the two consecutive four data, and latching an output of the multiplexer.

Finally, the third serialization step is for shifting the phase of one of the two consecutive four data by each data window of the eight serialized data, and the phase with the other of the two consecutive four data. Multiplexing the shifted data to output the serialized eight consecutive data. In addition, during a test operation or a training operation, the third serialization step may include outputting externally any data that is not synchronized with the system clock.

As described above, the data output circuit in the semiconductor memory device according to an embodiment of the present invention is parallel to 1.5 tCK before the data output time (that is, the cas delay time CL after the read command is applied). By serializing a large number of data outputs, it is possible to output data corresponding to high frequency system clocks and data clocks. In particular, in the case of a graphics semiconductor memory device in which fast data input and output are considered important, the operation of a high frequency system clock becomes possible, thereby improving product competitiveness.

In addition, the present invention has been described using the data output circuit in the semiconductor memory device as an example, but may be utilized in communication and network equipment for serializing and outputting data input in parallel.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

Claims (25)

First serializing means for serializing eight data input in parallel to output four consecutive two data; Second serialization means for receiving the output of the first serialization means and outputting two consecutive four data; And And third serialization means for receiving the output of said second serialization means and outputting eight serialized data. The method of claim 1, And each data window of the two consecutive data output from the first serialization means is four times each window of the eight serialized data. The method of claim 2, The first serialization means A phase shifter for shifting four of the eight data by four times the data window of the serialized eight data; A multiplexer for multiplexing the other four data of the eight data and the output of the phase shifter to output the four consecutive two data; And And a latch unit for latching an output of the multiplexer. The method of claim 3, wherein The phase shifter includes a plurality of unit phase shifters for shifting the phases of the four data, and each unit phase shifter An inverter for inverting input data; A transmission gate for transmitting an output of the inverter in response to a first control pulse; And And an inverter latch for latching, inverting, and outputting an output of the transfer gate. The method of claim 4, wherein The latch unit includes a plurality of unit latch units for latching the four consecutive two data outputs from the multiplexer, each unit latch unit A negative logic (NAND) gate for inverting and transferring each data in response to the data transmission signal; A transmission gate for transferring the output of the negative logical gate at intervals of four times each data window of the eight serialized data; And And an inverter latch for latching, inverting, and outputting an output of the transfer gate. The method of claim 3, wherein And a serialization controller for controlling the phase shifter, the multiplexer, and the latcher in response to a read data output signal for activating a data output in response to a read command and a data clock as a reference for the data output. . The method of claim 6, The serialization control unit A first latch for generating a first control pulse for controlling the phase shifter in response to the read data output signal; A second latch for generating a second control pulse having an activation period twice as long as a period of the data clock for controlling the multiplexer; And And a third latch for outputting a data transfer signal having an activation period of four times the period of the data clock for controlling the latch unit. The method of claim 1, And each data window of the four consecutive data output from the second serialization means is twice the respective window of the eight serialized data. The method of claim 8, The second serialization means A phase shifter for shifting two data of the four consecutive two data phases by twice the data window of the serialized eight data; A multiplexer for outputting the two consecutive four data by multiplexing the output of the phase shifter with another two data of the four consecutive two data; And And a latch unit for latching an output of the multiplexer. The method of claim 1, The third serialization means A phase shifter for shifting a phase of one of the two consecutive four data by each data window of the serialized eight data; And And a multiplexer for multiplexing the output of the phase shifter with the other of the two consecutive four data and outputting the eight serialized data. The method of claim 10, And during the test operation or the training operation, the phase shifter in the third serialization means outputs arbitrary data which is not synchronized with a system clock and transmits the multiplexer to the outside. The method of claim 11, The phase shifter A data inversion unit for inverting data in synchronization with the data clock; An asynchronous data generator for outputting the arbitrary data during the test operation or the training operation; And And an inverter latch for latching an output of the data inverting unit and the asynchronous data generating unit and outputting an inversion signal. First serializing means for receiving eight data inputted in parallel and outputting four consecutive two data having a data window four times as large as each window of the serialized eight data; Second serialization means for receiving two outputs of the first serialization means and outputting two consecutive four data having a data window twice that of each window of the eight serialized data; And And a third serialization means for receiving the output of the second serialization means and outputting the eight serialized data. The method of claim 13, Each of the first to third serialization means A phase shifter for shifting a phase by a window of data to output half of the input data; And And a multiplexer for generating the data to be output by multiplexing the other half of the input data and the output of the phase shifter. The method of claim 14, Each of the first and second serialization means further comprises a latch portion for latching and delivering the output of the multiplexer. The method of claim 13, And a serialization controller for controlling the first serialization means in response to a data enable signal for activating data transfer and a data clock as a reference for data output. The method of claim 16, The serialization control unit A first latch for generating a pulse having an activation period corresponding to a period of the data clock for controlling a phase shifter in the first serialization means in response to the data enable signal; A second latch for generating a pulse having an activation period twice as long as a period of said data clock for controlling a multiplexer in said first serialization means; And And a third latch for outputting a pulse having an activation interval of four times the period of the data clock for controlling the latch portion in the first serialization means. The method of claim 13, And the third serialization means outputs any data out of synchronization with the system clock during a test operation or a training operation. A first serialization step of outputting, as four consecutive two data, eight data transmitted from an internal unit cell corresponding to a read command and input in parallel; A second serialization step for outputting the four consecutive two data as two consecutive four data; And And a third serialization step for outputting the two consecutive four data as eight serialized data. The method of claim 19, And each data window of the two consecutive data output in the first serialization step is four times the respective windows of the eight serialized data. The method of claim 19, The first serialization step is Phase shifting four of the eight data by four times each data window of the serialized eight data; Multiplexing the other four data among the eight data and the four phase shifted data to output the four consecutive two data; And And latching the four contiguous two pieces of data. The method of claim 19, And each data window of the four consecutive data output in the second serialization step is twice the respective window of the eight serialized data. The method of claim 22, The second serialization step is Phase shifting two of the four consecutive two data phases by twice the data window of the serialized eight data; Multiplexing the other two data of the four consecutive two data and the phase shifted data and outputting the two consecutive four data; And And latching an output of the multiplexer. The method of claim 19, The third serialization step is Phase shifting one of the two consecutive four data by each data window of the serialized eight data; And And multiplexing the phase shifted data with the other one of the two consecutive four data to output the serialized eight consecutive data. The method of claim 19, In a test operation or a training operation, the third serialization step includes outputting externally any data that is not synchronized with the system clock.