CN1333356C - Write serialization and resource duplication combined multi-port register file design method - Google Patents
Write serialization and resource duplication combined multi-port register file design method Download PDFInfo
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- CN1333356C CN1333356C CNB2004100450813A CN200410045081A CN1333356C CN 1333356 C CN1333356 C CN 1333356C CN B2004100450813 A CNB2004100450813 A CN B2004100450813A CN 200410045081 A CN200410045081 A CN 200410045081A CN 1333356 C CN1333356 C CN 1333356C
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Abstract
The present invention discloses a design method for a multi-port register file of combined writing serialization and resource duplication, which aims to solve the technical problem that a design method for a multi-port register file having the characteristics of strong universality, small cost of hardware, high performance and short design period is not provided. The present invention has the technical scheme that a register file is designed into two parts, one part is a writing serialization part, and the other part comprises a storage body and a reading port part. A plurality of writing ports can be realized by a method of writing operation serialization in the writing serialization part; static RAM arranged in the design of FPGA and ASIC is utilized, and a plurality of reading ports can be realized by a method of resource duplication in the storage body and the reading part. The present invention has the advantages of strong universality, reduced complexity of design, reduced hardware needed in the realization of the design and improved performance.
Description
Technical field: the present invention relates in the integrated circuit (IC) design design and the implementation method of multiport register file in the design of register file design method, especially on-site programmable gate array FPGA and application-specific integrated circuit ASIC.
Background technology: microprocessor is the core component of current computer and embedded system.Along with the raising of integrated circuit technology level and the development of designing technique, the design of FPGA or ASIC has become the important component part of microprocessor Design and checking.Register file is a vitals of microprocessor, and the scale that characteristics of modern high performance microprocessor are register files is big, reading-writing port is many.In FPGA, use though also exist the static SRAM of single port or dual-port to can be used as register file, its port number can not directly use as multiport register file very little.In FPGA, realize multiport register file at present, generally adopt a kind of as
Www.fpgacpu.orgThe method of announcing that is called " Double Ram ", but this method hardware spending is big, and hardware consumption is difficult to stand after port surpasses some.In the ASIC design, the general method for designing that adopts full customization of multiport register file, yet technical threshold height, the design cycle of full Custom Design are long, are dissolved into the view that goes also must set up various complexity in the present ASIC design cycle in order to make full customized module.Therefore, concerning FPGA and ASIC design, seek and a kind ofly not only be applicable to FPGA but also be applicable to that the multiport register file method for designing of ASIC is the key issue that needs to be resolved hurrily.
Summary of the invention: the technical problem to be solved in the present invention is: at the problem that multiport register file design in present FPGA and the ASIC design exists, the method for designing of the multiport register file that provide a kind of highly versatile, hardware spending is little, performance is high, the design cycle is short.
Technical scheme of the present invention is that register file design is become two parts, and a part is to write the serial parts, and a part is memory bank and read port parts.In writing the serial parts, adopt the serialized method of write operation to realize a plurality of write ports; The static RAM (SRAM) that provides in FPGA and the ASIC design is provided, and the method by resources duplication in memory bank and read port parts realizes a plurality of read ports.One has the specific design method of the multiport register file of m read port and n write port to be:
1. determine the implementation method of single port register file, in FPGA, the single port register file is realized by distributed RAM; In the ASIC design, the single port register file generates with memory bank compiler (MemoryCompiler) compiling.The single port register file is the register file with a read port and a write port, and read port comprises to be read the address and read enable signal input end, read data output terminal; Write port comprises write data, write address, writes the enable signal input end.
2. in writing the serial parts, adopt and write n the write port that the serialization method realizes register file, write the serial parts and form by n bank of latches, a mould k counter and a MUX:
1) bank of latches of n group by the major clock clk control of system is set, a bank of latches is made up of data latches, address latch and enable signal latch, the rising edge of system clock clk with data, the address of n write port, write enable signal and be latched into n group bank of latches respectively, promptly the data of the 1st write port are write the write data latch device that is latched into bank of latches 1; The address latch of the 1st write port is to the write address latch of bank of latches 1; The 1st write port write the enable latch of writing that enable signal is latched into bank of latches 1; The data of the 2nd write port are write the write data latch device that is latched into bank of latches 2; The address latch of the 2nd write port is to the write address latch of bank of latches 2; The 2nd write port write the enable latch of writing that enable signal is latched into bank of latches 2; ... and the like, the data of n write port are write the write data latch device that is latched into bank of latches n; The address latch of n write port is to the write address latch of bank of latches n; N write port write the enable latch of writing that enable signal is latched into bank of latches n.The data of supposing write port are a position, and the address is the b position, and enable signal is 1, and then a bank of latches is (a+b+1) individual latch.
2) a mould k counter by clock clk_fast control is set, k 〉=n, the frequency of clock clk_fast be clock clk frequency k doubly, after the rising edge of clk, the value of mould k counter is 0, adds 1 counting thereafter.
3) MUX by mould k counter controls is set.MUX selects 1 MUX to form by 3 n, is respectively write data, write address, writes the enable signal MUX.The input of MUX comes from n group latch, under the control of mould k counter, at quick clock
Clk_fastEach bat, select a bank of latches respectively, with wherein write data, write address and write enable signal and deliver to memory bank and read port parts.The currency that makes mould k counter is cur_count, and when cur_count=i, the output of i group latch is selected; When cur_count=i+1, the output of i+1 group latch is selected; And the like, when cur_count=i+n-2, the output of n-1 group latch is selected; When cur_count 〉=i+n-1, the output of n group latch is selected, wherein i 〉=0 and i≤k-n.
3. adopt the resources duplication method to realize m read port of register file in memory bank and read port parts: memory bank and read port parts are made up of m single port register file.The write data of m single port register file, write address and write the enable signal input end all respectively with write data, write address, write the output that enables MUX and link to each other.Under the control of quick clock clk_fast, each data of clapping a write port writes m single port register file simultaneously, like this, the data of n write port just are written in m the single port register file successively serially simultaneously, because write data, the write address of m single port register file and the signal of writing the connection of enable signal input end all are the same, therefore the data of their storages are the same, have guaranteed m the data consistent that read port has access to.The m of a multiport register file of the present invention read port is corresponding one by one with m single port register file, the data that read the address of i read port of multiport register file and read enable signal and be connected respectively to i single port register file and read the address and read to enable input end, i single port register file are i the data that read port is read just.
Adopt the present invention can produce following useful technique effect:
1. the present invention both had been applicable to the design of the register file of FPGA, was applicable to the design of the register file of ASIC again, highly versatile.
2. the resource that can provide in FPGA and the ASIC design has been provided, has reduced the complexity of design.
3. pass through the write operation serialization, a write port of single port register file is shared in a plurality of write port timesharing, and the hardware spending of having avoided a plurality of write ports of direct realization to bring has reduced the hardware that the design realization needs.
4. by resources duplication, simplify the design realization of read port, and can guarantee effectively that the data that read port has access to are consistent, improved performance.
Description of drawings:
Fig. 1 is a building-block of logic with register file of m read port and n write port that adopts the present invention to realize;
Embodiment:
Fig. 1 is a building-block of logic with register file of m read port and n write port that adopts the present invention to realize.The present invention becomes two parts with register file design, and a part is to write the serial parts, and a part is memory bank and read port parts.Writing the serial parts is made up of the counter of n bank of latches, a MUX and a mould k.The number of bank of latches equates with the write port number, each bank of latches is made up of a data latch, a b address latch and 1 enable signal latch, and the rising of system clock clk or negative edge are with data, the address of write port and write enable signal and latch respectively.MUX in each bat of clock clk_fast fast, is selected a bank of latches respectively under the control of mould k (k is a number that is not less than n) counter, wherein data, address and enable signal are delivered to memory bank and read port parts.Memory bank and read port parts are made up of m single port register file, and the single port register file is the register file with a read port and a write port, and read port comprises to be read the address and read enable signal input end, read data output terminal; Write port comprises write data, write address, writes the enable signal input end.M is the number of read port.The write data of m single port register file, write address and write the enable signal input end all respectively with write data, write address, write the output that enables MUX and link to each other.Under the control of quick clock clk_fast, each data of clapping a write port writes m single port register file.Because write data, the write address of m single port register file all are the same with the signal of writing the connection of enable signal input end, so the data that their are stored also are the same.The m of a multiport register file of the present invention read port is corresponding one by one with m single port register file, the data that read the address of i read port of multiport register file and read enable signal and be connected respectively to i single port register file and read the address and read to enable input end, i single port register file are i the data that read port is read just.
The present invention adopts in the functional verification of the dsp chip FT-C62 that University of Science and Technology for National Defence develops voluntarily.In the FPGA of FT-C67 CPU core simulating, verifying, adopt the present invention in a slice FPGA, to realize comprising two 10 CPU core of reading 6 register files of writing.Before adopt the present invention, singly be 80% the resource of the register file FPGA VirtexII xcv4000 that just taken 4,000,000 in Xilinx company; Adopt the present invention, two register files have only taken about 40% resource altogether.
Claims (1)
1. write the multiport register file method for designing that serialization and resources duplication combine for one kind, it is characterized in that register file design is become two parts, a part is to write the serial parts, a part is memory bank and read port parts, adopts the serialized method of write operation to realize a plurality of write ports in writing the serial parts; The static RAM (SRAM) that provides in FPGA and the ASIC design is provided, and the method by resources duplication in memory bank and read port parts realizes a plurality of read ports, and one has the specific design method of the multiport register file of m read port and n write port to be:
1.1 determine the implementation method of single port register file, in FPGA, the single port register file is realized by distributed RAM; In the ASIC design, the single port register file generates with the compiling of memory bank compiler, and the single port register file is the register file with a read port and a write port, and read port comprises to be read the address and read enable signal input end, read data output terminal; Write port comprises write data, write address, writes the enable signal input end;
1.2 in writing the serial parts, adopt and write n the write port that the serialization method realizes register file, write the serial parts and form by n bank of latches, a mould k counter and a MUX:
1.2.1 the bank of latches of n group by the major clock clk control of system is set, a bank of latches is made up of data latches, address latch and enable signal latch, the rising of system clock clk or negative edge with data, the address of n write port, write enable signal and be latched into n group bank of latches respectively, the data of write port are a position, the address is the b position, enable signal is 1, and then a bank of latches is (a+b+1) individual latch;
1.2.2 a mould k counter by clock clk_fast control is set, k 〉=n, the frequency of clock clk_fast be clock clk frequency k doubly, after the rising edge of clk, the value of mould k counter is 0, adds 1 counting thereafter;
1.2.3 a MUX by mould k counter controls is set, and MUX selects 1 MUX to form by 3 n, is respectively write data, write address, writes the enable signal MUX; The input of MUX comes from n group latch, under the control of mould k counter, in each bat of clock clk_fast fast, selects a bank of latches respectively, with wherein write data, write address and write enable signal and deliver to memory bank and read port parts; The currency that makes mould k counter is cur_count, and when cur_count=i, the output of i group latch is selected; When cur_count=i+1, the output of i+1 group latch is selected; And the like, when cur_count=i+n-2, the output of n-1 group latch is selected; When cur_count 〉=i+n-1, the output of n group latch is selected, wherein i 〉=0 and i≤k-n;
1.3 adopt the resources duplication method to realize m read port of register file in memory bank and read port parts: memory bank and read port parts are made up of m single port register file, the write data of m single port register file, write address and write the enable signal input end all respectively with write data, write address, write the output that enables MUX and link to each other; Under the control of quick clock clk_fast, each data of clapping a write port writes m single port register file simultaneously, like this, the data of n write port just are written in m the single port register file successively serially simultaneously, because write data, the write address of m single port register file and the signal of writing the connection of enable signal input end all are the same, therefore the data of their storages are the same, have guaranteed m the data consistent that read port has access to; The m of a multiport register file read port is corresponding one by one with m single port register file, the data that read the address of i read port of multiport register file and read enable signal and be connected respectively to i single port register file and read the address and read to enable input end, i single port register file are i the data that read port is read just.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11175394A (en) * | 1997-12-11 | 1999-07-02 | Nec Corp | Information processor and multi-port register file |
| US20010011342A1 (en) * | 1998-07-09 | 2001-08-02 | Pechanek Gerald G. | Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision |
| US6343348B1 (en) * | 1998-12-03 | 2002-01-29 | Sun Microsystems, Inc. | Apparatus and method for optimizing die utilization and speed performance by register file splitting |
| CN1501292A (en) * | 2002-09-11 | 2004-06-02 | �����ɷ� | High-level synthesis method for producing the explanation of digital circuit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11175394A (en) * | 1997-12-11 | 1999-07-02 | Nec Corp | Information processor and multi-port register file |
| US20010011342A1 (en) * | 1998-07-09 | 2001-08-02 | Pechanek Gerald G. | Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision |
| US6343348B1 (en) * | 1998-12-03 | 2002-01-29 | Sun Microsystems, Inc. | Apparatus and method for optimizing die utilization and speed performance by register file splitting |
| CN1501292A (en) * | 2002-09-11 | 2004-06-02 | �����ɷ� | High-level synthesis method for producing the explanation of digital circuit |
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