KR940016923A - Source / drain region formation method of semiconductor device - Google Patents

Source / drain region formation method of semiconductor device Download PDF

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Publication number
KR940016923A
KR940016923A KR1019920027080A KR920027080A KR940016923A KR 940016923 A KR940016923 A KR 940016923A KR 1019920027080 A KR1019920027080 A KR 1019920027080A KR 920027080 A KR920027080 A KR 920027080A KR 940016923 A KR940016923 A KR 940016923A
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KR
South Korea
Prior art keywords
forming
source
drain region
semiconductor device
insulating film
Prior art date
Application number
KR1019920027080A
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Korean (ko)
Inventor
노승정
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027080A priority Critical patent/KR940016923A/en
Publication of KR940016923A publication Critical patent/KR940016923A/en

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 소자의 소오스/드레인 영역을 형성할 때 실리콘 기판을 이온 확산 측면에서 비교적 낮은 온도인 약 450℃ 정도로 유지함으로써, 셀프 어닐링 현상으로 인하여 이온주입시 발생되는 실리콘 결함을 방지하여, 추가 또는 부수적인 고온 공정을 필요로 하지 않고 낮은 접합을 형성한다.When forming the source / drain regions of the semiconductor device, the silicon substrate is maintained at about 450 ° C., which is a relatively low temperature in terms of ion diffusion, thereby preventing silicon defects generated during ion implantation due to self-annealing, and thus additional or incidental high temperature. Forms low junctions without the need for a process.

Description

반도체 소자의 소오스/드레인 영역 형성 방법Source / drain region formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 5 도는 콘택 측벽의 절연막을 제외하고 전 절연막을 제거하는 상태를 나타내는 반도체 소자의 단면도. 제 6 도는 전체구조 상부로부터 이온주입공정을 이행하여 소오스/드레인 영역을 형성하는 단계를 나타내는 반도체 소자의 단면도. 제 7 도는 전체구조 상부로부터 금속배선 및 패시베이숀 막을 형성하는 단계를 나타내는 반도체 소자의 단면도.5 is a cross-sectional view of a semiconductor device showing a state in which all insulating films are removed except the insulating film on the contact sidewall. 6 is a cross-sectional view of a semiconductor device showing a step of forming a source / drain region by performing an ion implantation process from the top of the overall structure; 7 is a cross-sectional view of a semiconductor device showing the step of forming a metallization and passivation film from above the entire structure.

Claims (2)

실리콘 기판(1)상에 게이트 절연막(2) 및 게이트(3)를 형성하는 단계와, 상기 게이트(3)상에 층간절연막(4) 및 평탄화 막(5)을 순차적으로 형성하는 단계와, 상기 층간 절연막(4) 및 평탄화 막(5)의 소정부분을 식각하여 콘택을 형성하는 단계와, 전체구조 상부에 절연막(6)을 소정 두께로 형성하는 단계와, 상기 콘택측벽을 제외하고 전체 절연막(6)을 제거하는 단계와, 전체구조 상부로부터 이온을 주입하여 상기 실리콘 기판(1)의 소정 부분에 소오스/드레인 영역(10)을 형성하는 단계와, 전체구조 상부에 금속배선(8) 및 패시 베이숀 막(9)을 형성하는 단계를 포함하는 반도체 소자의 소오스/드레인 영역 형성 방법에 있어서, 소오스/드레인 영역(10)을 형성하기 위해 이온 주입 실리콘 기판(1)을 낮은 온도로 높인 상태로 유지하여 낮은 접합을 형성하는 것을 특징으로 하는 반도체 소자의 소오스/드레인 영역 형성 방법.Forming a gate insulating film (2) and a gate (3) on the silicon substrate (1), sequentially forming an interlayer insulating film (4) and a planarization film (5) on the gate (3), and Etching a predetermined portion of the interlayer insulating film 4 and the planarization film 5 to form a contact, forming an insulating film 6 on the entire structure to a predetermined thickness, and forming a whole insulating film except for the contact side wall ( 6) removing, implanting ions from the top of the entire structure to form a source / drain region 10 in a predetermined portion of the silicon substrate 1, metal wiring 8 and passivation over the entire structure A method of forming a source / drain region of a semiconductor device comprising forming a bastion film 9, wherein the ion implanted silicon substrate 1 is raised to a low temperature to form the source / drain region 10. Holding to form a low junction Source / drain regions The method of forming a semiconductor device of a. 제 1 항에 있어서, 상기 낮은 온도는 450℃ 정도인 것을 특징으로 하는 반도체 소자의 소오스/드레인 영역 형성 방법.The method of claim 1, wherein the low temperature is about 450 ° C. 3. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027080A 1992-12-31 1992-12-31 Source / drain region formation method of semiconductor device KR940016923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027080A KR940016923A (en) 1992-12-31 1992-12-31 Source / drain region formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027080A KR940016923A (en) 1992-12-31 1992-12-31 Source / drain region formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR940016923A true KR940016923A (en) 1994-07-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027080A KR940016923A (en) 1992-12-31 1992-12-31 Source / drain region formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR940016923A (en)

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