KR940016833A - Dynamic ram cell - Google Patents
Dynamic ram cell Download PDFInfo
- Publication number
- KR940016833A KR940016833A KR1019920026924A KR920026924A KR940016833A KR 940016833 A KR940016833 A KR 940016833A KR 1019920026924 A KR1019920026924 A KR 1019920026924A KR 920026924 A KR920026924 A KR 920026924A KR 940016833 A KR940016833 A KR 940016833A
- Authority
- KR
- South Korea
- Prior art keywords
- cell
- transistor
- dynamic ram
- line
- capacitor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Abstract
본 발명은 DRAM 셀에서 스토리지 캐패시턴스를 줄일 수 있는 새로운 DRAM 셀 회로에 관한 것으로, 특히 한개의 트랜지스터와 한개의 캐패시터를 사용하여 구현한 새로운 다이나믹 램 셀에 관한 것으로, 한개의 트랜지스터와 한개의 캐패시터를 사용하여 구현한 새로운 다이나믹 램 셀은 ; DRAM 셀의 선택을 위한 연결선으로 사용하는 워드라인(2)에 게이트가 연결되는 셀 트랜지스터(3), 상기 셀 트랜지스터(3)의 드레인 단자(7)와 DRAM 셀의 정보를 읽고 쓰기 위한 연결선으로 사용하는 비트 라인(1)의 사이에 연결되어 정보저장을 위한 소자로 이용되는 스토리지 캐패시터(5)로 구성된 것을 특징으로 한다.The present invention relates to a new DRAM cell circuit that can reduce storage capacitance in a DRAM cell, and more particularly, to a new dynamic RAM cell implemented using one transistor and one capacitor, using one transistor and one capacitor. The new dynamic RAM cell implemented by Cell transistor 3 having a gate connected to a word line 2 used as a connection line for selecting a DRAM cell, and a drain line 7 of the cell transistor 3 and a connection line for reading and writing information of a DRAM cell. It is characterized by consisting of a storage capacitor 5 is connected between the bit line (1) used as an element for storing information.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 2 도는 본 발명에 따른 DRAM 셀의 구성도.2 is a block diagram of a DRAM cell according to the present invention.
Claims (1)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92026924A KR960008530B1 (en) | 1992-12-30 | 1992-12-30 | Dram cell |
JP5336496A JPH06232370A (en) | 1992-12-30 | 1993-12-28 | Dynamic ram cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92026924A KR960008530B1 (en) | 1992-12-30 | 1992-12-30 | Dram cell |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940016833A true KR940016833A (en) | 1994-07-25 |
KR960008530B1 KR960008530B1 (en) | 1996-06-26 |
Family
ID=19348078
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR92026924A KR960008530B1 (en) | 1992-12-30 | 1992-12-30 | Dram cell |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH06232370A (en) |
KR (1) | KR960008530B1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6337497B1 (en) * | 1997-05-16 | 2002-01-08 | International Business Machines Corporation | Common source transistor capacitor stack |
US6201730B1 (en) * | 1999-06-01 | 2001-03-13 | Infineon Technologies North America Corp. | Sensing of memory cell via a plateline |
US8743591B2 (en) * | 2011-04-26 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device and method for driving the same |
JP5901927B2 (en) * | 2011-10-06 | 2016-04-13 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS594158A (en) * | 1982-06-30 | 1984-01-10 | Fujitsu Ltd | Semiconductor memory device |
JPS6130065A (en) * | 1984-07-23 | 1986-02-12 | Nec Corp | Semiconductor memory cell |
JPS61140172A (en) * | 1984-12-13 | 1986-06-27 | Toshiba Corp | Semiconductor memory device |
JPS61150366A (en) * | 1984-12-25 | 1986-07-09 | Nec Corp | Mis type memory cell |
JP2519216B2 (en) * | 1986-08-20 | 1996-07-31 | 株式会社東芝 | Semiconductor memory device |
JPH06105770B2 (en) * | 1988-02-04 | 1994-12-21 | 日本電気株式会社 | Dynamic semiconductor memory device |
-
1992
- 1992-12-30 KR KR92026924A patent/KR960008530B1/en not_active IP Right Cessation
-
1993
- 1993-12-28 JP JP5336496A patent/JPH06232370A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
KR960008530B1 (en) | 1996-06-26 |
JPH06232370A (en) | 1994-08-19 |
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G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060522 Year of fee payment: 11 |
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LAPS | Lapse due to unpaid annual fee |