JPS6130065A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To provide a cell which does not result in soft errors, by providing with a P type region having a higher concentration and a P type region having an end extruded and having a lower concentration than a comparatively low impurity concentration of an N type region, which are contacted each other and cause the N type region to be underlaid, on a P type Si substrate, and by connecting a word wire to the lower concentration P type region and a bit wire to the higher concentration P type region. CONSTITUTION:A P type region 102 having an impurity concentration of about 2X10<17>/cm<3> and having an end extruded and a P type region 104 having a concentration above 10<18>/cm<3>, contacting with each other, are formed with an N type region 103 with a concentration of about 2X10<17>/cm<3> underlain on a P type Si substrate 101 with a concentration of about 2X10<15>/cm<3>. Next, at the end of the regions 103, 104, an N type region 107 with a concentration above 10<18>/cm<3> for supplying a reference voltage is formed, and on the region 102 a conductive film 105 serving as both of a gate electrode and a word wire is formed with a gate insulating film 106 interposed. Moreover, on the region 104, a bit wire 110 is coated with a conductive film 108 and an insulating film 109 for forming a capacitance interposed. Thus invasion of radioactive particles can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory cell that is less susceptible to soft errors caused by radioactive particles such as alpha particles even when downsized.

(Prior art and its problems) When radioactive particles such as alpha particles enter a semiconductor, a large amount of electric charge is generated inside the semiconductor. When these charges flow into the electrodes inside the semiconductor memory cell, they change the potential of the electrodes, resulting in soft errors. When the amount of charge handled by the electrodes in a semiconductor memory cell is large, the influence of such an inflow of internally generated charges is small, and this memory cell rarely causes soft errors. However, when semiconductor memory cells are reduced in size, the amount of charge handled by the electrodes in the memory cells decreases, so the problem of soft errors becomes serious.

In conventional semiconductor memory cells, the structure of the electrode in the memory cell is improved to reduce the flow of charge generated by radioactive particles into this electrode, and to keep the amount of charge handled by this electrode greater than the amount of charge flowing in. This prevented soft errors.

For example, the 1981 International Conference on Electronic Devices (IBDM')
81) Proceedings pages 40-43 - ABu-ri
ed N-Grid for Protecti
on Agalnst Ra-dlatlon I
duced Charge Co11ectio
n InElectronic C1rcuits
”, by M.R. Waldemann (M-R-Wo
In the method proposed by P
The N-type lattice-like region embedded inside the mold substrate collects carriers generated by radioactive particles and attempts to reduce the amount of charge flowing into the electrodes in the memory cell. on the other hand,
IEgB Journal of 8o11d-
5C-18 of 8tate C4rcuits, Volume 5
Papers published on pages 457-463 of issue ”A
70ns High DensitV64K 0MO
In the memory cell reported by R. J. C. Chwang et al. in ``8Dynamic RAM'', the internal electrodes of the memory cell are formed in the N-well to reduce the amount of energy generated by radioactive particles. An attempt is made to reduce the amount of carriers that flow into the internal electrodes of memory cells.

However, the buried lattice region is formed at a depth of 2.2 μm from the surface, and the depth of the N well is 4.5 μm.
Met. Therefore, the charges generated by radioactive particles that can be removed by these buried layers and wells are limited to those generated at a depth of about 1 μm or 2 μm from the substrate surface, respectively, and charges generated at shallower depths are removed. It was not possible to remove it. The amount of charge generated in the 1-2 μm region of the surface is on the order of 1×10” clones for α particles.
This is not a small value for an 8I memory cell and can have a significant impact.

If the buried layer or well can be made shallower, the amount of radioactive particle generated charge that can be removed by these can be increased. However, in the conventional structure, the characteristics of the MOSFET formed on the surface of the substrate are affected by the buried layer and the well, so that it is not possible to form them shallowly.

(Objective of the Invention) An object of the present invention is to provide a semiconductor memory cell that is less susceptible to soft errors and can sufficiently reduce the amount of charge generated by radioactive particles such as alpha particles that flows into the internal electrode of the memory cell. It is to be.

(Structure of the Invention) A semiconductor memory cell according to the present invention includes a first region of a second conductivity type formed on the main surface of a semiconductor substrate of a first conductivity type;
A second region that is in contact with the region and has a higher carrier concentration than the first region.
a second region of conductivity type; a third region of first conductivity type that is in contact with the first region and the second region and is isolated from the first conductivity type substrate region; and a third region of the first conductivity type that straddles at least the first region.
It is characterized by having an electrode formed on the surface of the region extending from the conductive type substrate region to the third region via an insulating film.

(Example: Configuration) Next, the structure and effects of the semiconductor memory cell of the present invention will be explained using an example of the present invention.

FIG. 1 shows the structure of an embodiment of a semiconductor memory cell according to the present invention.
) is cut open at 114jl14'. 101 is a P-type silicon crystal substrate, 102 is an N-type first region, 103 is an N-type second region having a higher carrier concentration than the N-type first region, and 104 is a P-type silicon crystal substrate isolated from the P-type substrate. 105 is a conductive film that serves as the gate electrode and word line of the MOSFET, 106 is a gate insulator film of the MOSFET, 107 is an N-type fourth region supplied with a reference potential, and 108 is a P-type third region. 109 is an insulating film that forms a capacitance between the conductors 108 and 110, 110 is a conductive film that becomes a bit line, 111 is an insulator, 112 is an element isolation region, and 113 is a P Mold third area 1
04 and a contact hole for connecting the conductor film 108,
are shown respectively. Here, for example, the impurity concentration of the P-type substrate 101 is approximately 2×IQ"cm-", and the N-type first region 1
02 impurity concentration 2□X I Q"am", N type 2nd
The impurity concentration of the region 103 is set to approximately 2X IQ"tx-",
The impurity concentration of the P-type third region 104 and the N-type fourth region 107 is set to 101 or more.

The structure of FIG. 1 constitutes a memory cell whose equivalent circuit is shown in FIG. The 112th digit of the numbers indicating each part in FIG. 2 corresponds to that in FIG. 201, 207 in Figure 2
204 is a memory cell internal electrode which becomes electrically floating during information storage, 205 is a word line, 209 is a cell capacitor, and 210 is a bit line. Reference numeral 215 indicates a P-type channel MO8FET in which 105 in FIG. 1 is a gate electrode, 101 and 104 are conduction electrodes, and 102 and 103 are substrate regions.

The circuit shown in FIG. 2 is the same as the circuit configuration of the memory cell described in, for example, Japanese Patent Publication No. 10864/1983. 2
The forward information is stored by the amount of charge stored in the cell capacitor 209. MO8F'ET 2 when writing and reading
15 is turned on, charge is set from the bit line 210 to the cell capacitor 209, and charge is discharged from the cell capacitor 209 to the bit line 210. MOSFET 2 when storing information
15 is turned off, and the charge stored in the cell capacitor 209 is conserved.

(Example: Principle and Effect) In the memory cell shown in FIG.
The amount of radioactive particle generation holes flowing into the die-sinking 3 region 104 is related to the soft error. N-type region 102 jlo
3 The holes generated at p 1.07 are in the P-type substrate 101.
Therefore, it is considered that the holes generated from the surface of each N-type region to about half the depth of the region flow into the P-type engraving 3 region 104. . From this, it follows that the thinner the N-type region 102 #103, 107 surrounding the P-type engraving 3 region 104 is, the less likely it is that soft rainbows will occur due to radioactive particles.

On the other hand, in order for the memory cell shown in Figure 1 to operate normally,
The P-type engraving region 104 must be electrically insulated from the P-type substrate 101. For example, P die engraving 3 area 104 and P
Let us consider a case where the voltage applied between the mold substrates 101 is about 5V.

In the memory cell shown in FIG. 1, the N-type second region 103 and the N-type fourth region
Since the impurity concentration in the regions 107 is sufficiently high, even if their thickness is reduced to 0.2 to 0.3 μm, the insulation between the P-type engraving 3 region 104 and the P-type substrate 101 in these regions is sufficient. . On the other hand, the pm third region in the N-type first region 102
Although the impurity concentration in the N-type first region 102 is low, the insulation between the region 104 and the P-type substrate 101 can be controlled by the potential of the gate electrode 105 because the voltage in this portion can be controlled by the potential of the gate electrode 105.

Even if the thickness of the N-type first region 102 is 0.2 to 0.3 μm
Even if the MOSFET in this part is thin, if a voltage that turns off the MOSFET in this part is supplied to the gate electrode 105, the P in this part can be reduced.
Sufficient insulation can be achieved between the die engraving region 104 and the P-type substrate 101.

In order to perform a write/read operation on the memory cell shown in FIG. 1, the threshold voltage of the MOSFET must be an appropriate value, for example, about -1V.

However, in the memory cell shown in FIG.
Since the impurity concentration of the MO8FFIT can be lowered independently of the thickness of the region, the threshold voltage of the MO8FFIT can be easily set to an appropriate value. When using the N-well described as an example of the prior art, the impurity concentration of the N-well is equal to that of the MOSFET.
The depth was determined so that the threshold voltage of the memory cell could be set to an appropriate value, and the depth was determined so that the internal electrode of the memory cell could be insulated from the substrate.

Therefore, the impurity concentration is low and the depth is 4.5 μm.
I had to go deeper. However, in the memory cell of the present invention, the impurity concentration can be lowered only under the gate of the MOSFET, and the impurity concentration in the other N-type regions surrounding the P-type carved region 104, which becomes the cell internal electrode, can be increased, and the thickness can be reduced to 0.
．． It can be made as thin as 2 to 0.3 μm. As a result, the amount of charge generated by radioactive particles flowing into the internal electrodes of the memory cell is reduced to 1/2 compared to the conventional one.
It can be reduced to 10 or less, which has almost no effect.

(Example: Manufacturing method) The structure of the memory cell shown in FIG. 1 can be formed by a method as shown in FIG. 3, for example. FIG. 3 (,) shows that the surface of a P-type silicon crystal substrate 301 with an impurity concentration of approximately 2 X 10" This shows the formation of an N-type region 302.

Figure 3(b) shows that using high-energy ion implantation,
The impurity concentration inside the substrate is about 2 x 101? ex-”N
A mold region 303 is shown formed.

FIG. 3(c) shows a P-type region 304, N
The respective formed mold regions 307 are shown.

Thereafter, by forming a gate insulator film, gate electrode, wiring, etc., a structure as shown in FIG. 1 is obtained.

In the semiconductor memory cell of the present invention, the impurity concentration in each region has an important meaning. It should be noted that the impurity concentration in the present invention refers to an impurity concentration that is meaningful as a semiconductor, and also refers to an active impurity concentration that is closely related to the N-type or P-type carrier concentration. .

(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a semiconductor memory cell that is small in size and has fewer soft errors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the structure of a semiconductor memory cell according to the present invention, in which (a) is a horizontal view, and (b) is a 114*11
FIG. 4 is a cross-sectional view cut open at 4'. FIG. 2 is an equivalent circuit diagram of the embodiment shown in FIG. 3(a) to 3(c) are cross-sectional views showing an example of a manufacturing process for producing the structure of the embodiment shown in FIG. 1. 101... P-type silicon crystal substrate 102...-N-type first region 103... N-type second region 104... P-type third region 105... Conductor film 10
6... Gate insulator film 107... N-type fourth region 108 supplied with reference potential
...Conductor film 109...Insulator film 110...
・Conductor film 111-...Insulator Figure 1 Figure 2

Claims (1)

[Claims] a first region of a second conductivity type formed on the main surface of a semiconductor substrate of a first conductivity type; a second region of a second conductivity type that is in contact with the first region and has a higher carrier concentration than the first region; a third region of the first conductivity type that is in contact with the first conductivity type substrate region and the second region and is isolated from the first conductivity type substrate region;
A semiconductor memory cell comprising an electrode formed on a surface of a region extending from the first conductivity type substrate region to the third region via an insulating film.