KR940015869A - Peripheral logic control circuit using DMA of CPU - Google Patents

Peripheral logic control circuit using DMA of CPU Download PDF

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Publication number
KR940015869A
KR940015869A KR1019920026994A KR920026994A KR940015869A KR 940015869 A KR940015869 A KR 940015869A KR 1019920026994 A KR1019920026994 A KR 1019920026994A KR 920026994 A KR920026994 A KR 920026994A KR 940015869 A KR940015869 A KR 940015869A
Authority
KR
South Korea
Prior art keywords
cpu
logic control
dma
control circuit
peripheral logic
Prior art date
Application number
KR1019920026994A
Other languages
Korean (ko)
Inventor
윤필수
Original Assignee
백중영
금성통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 백중영, 금성통신 주식회사 filed Critical 백중영
Priority to KR1019920026994A priority Critical patent/KR940015869A/en
Publication of KR940015869A publication Critical patent/KR940015869A/en

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Abstract

본 발명은 CPU 주변 로직 컨트롤을 DMA 기능을 이용 시스템 효율 및 데이타 처리를 신속하게 목적이 있다.An object of the present invention is to use the DMA function of the CPU peripheral logic control, the system efficiency and data processing quickly.

메모리의 구성을 가진 주변로직 다수개를 프로세서에 연결되어 사용하고저 할때 아래그림과 같이 CPU가 하나 하나를 제어하는 방법으로 하면 프로세서의 프로그램 효율이 떨어지게 된 것이다.When a number of peripheral logics with a memory configuration are connected to the processor and used, as shown in the figure below, the CPU controls one by one, which reduces the program efficiency of the processor.

Description

CPU의 DMA를 이용한 주변로직 제어회로Peripheral logic control circuit using DMA of CPU

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 제 본 발명 주변로직 제어 시스템 구성도, 제3도는 제2도 주변 드바이스의 메모리 구성도, 제4도는 제2도의 상세 구성도.2 is a configuration diagram of the peripheral logic control system of the present invention, FIG. 3 is a memory configuration diagram of a peripheral device, and FIG. 4 is a detailed configuration diagram of FIG.

Claims (1)

CPU의 DMA기능을 이용하기 위해서 각각의 어드레스를 연속적으로 구성하고, 디코드 G1,G2, G3을 통해서 나오는 어드레스를 변환하는 조직 구성하는 컨트롤.In order to take advantage of the DMA function of the CPU, each address is continuously configured, and an organizational control for converting the addresses through the decodes G1, G2, and G3 is performed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920026994A 1992-12-30 1992-12-30 Peripheral logic control circuit using DMA of CPU KR940015869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026994A KR940015869A (en) 1992-12-30 1992-12-30 Peripheral logic control circuit using DMA of CPU

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026994A KR940015869A (en) 1992-12-30 1992-12-30 Peripheral logic control circuit using DMA of CPU

Publications (1)

Publication Number Publication Date
KR940015869A true KR940015869A (en) 1994-07-21

Family

ID=67214907

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920026994A KR940015869A (en) 1992-12-30 1992-12-30 Peripheral logic control circuit using DMA of CPU

Country Status (1)

Country Link
KR (1) KR940015869A (en)

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