KR900013390A - Microprocessor - Google Patents

Microprocessor Download PDF

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Publication number
KR900013390A
KR900013390A KR1019900001965A KR900001965A KR900013390A KR 900013390 A KR900013390 A KR 900013390A KR 1019900001965 A KR1019900001965 A KR 1019900001965A KR 900001965 A KR900001965 A KR 900001965A KR 900013390 A KR900013390 A KR 900013390A
Authority
KR
South Korea
Prior art keywords
register
registers
windows
storage means
microprocessor
Prior art date
Application number
KR1019900001965A
Other languages
Korean (ko)
Other versions
KR920006789B1 (en
Inventor
겐지 사카우에
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR900013390A publication Critical patent/KR900013390A/en
Application granted granted Critical
Publication of KR920006789B1 publication Critical patent/KR920006789B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
  • Microcomputers (AREA)

Abstract

내용 없음No content

Description

마이크로 프로세서Microprocessor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 1실시예에 따른 마이크로프로세서의 블록도,1 is a block diagram of a microprocessor according to an embodiment of the present invention;

제4도는 파이프라인구조의 개략 설명도이다.4 is a schematic explanatory diagram of a pipeline structure.

Claims (3)

복수개의 레지스터원도우(101, 102)를 갖추고 있고 이 각각의 레지스터윈도우(101, 102)가 복수의 레지스터를 구비하고 있으며, 프로그램상의 개개의 프로시저에 대해 상기 레지스터윈도우(101, 102)중의 어느 하나를 선택적으로 할당하여 어떤 프로시저에서 사용하는 작업레지스터(101, 102)를 결정하는 마이크로프로세서에 있어서, 상기 각 레지스터는 복수의 레지스터윈도우(101, 102)에 공통으로 할당되어 있고, 또한 사익 각 레지스터윈도우(101, 102)를 구성하는 레지스터수를 기억하는 기억수단(108)이 구비되어 있으며, 이 기억수단(108)내에 기억되어 있는 구성레지스터수를 기초로 하여 상기 레지스터윈도우(101, 102)가 상기 레지스터중의 어느 것에 의해 구성되는가가 결정되는 것을 특징으로 하는 마이크로세서.A plurality of register windows 101 and 102 are provided, and each of the register windows 101 and 102 includes a plurality of registers, and any one of the register windows 101 and 102 for each procedure in the program. In the microprocessor for selectively assigning the number of registers to determine the working register (101, 102) to be used in a procedure, each register is commonly assigned to a plurality of register windows (101, 102) A storage means 108 is provided for storing the number of registers constituting the windows 101 and 102, and the register windows 101 and 102 are based on the number of configuration registers stored in the storage means 108. Which of the registers is determined is determined. 제1항에 있어서, 상기 기억수단(108)에 상기 구성레지스터수가 상기 작업레지스터에 대한 어드레스정보를 기초로 하여 자동적으로 기억되는 것을 특징으로 하는 마이크로프로세서.2. The microprocessor according to claim 1, wherein the number of component registers is automatically stored in the storage means (108) based on the address information for the work register. 제1항에 있어서, 상기 기억수단(108)에 상기 구성레지스터수가 실행가능한 명령의 하나를 기초로 하여 기억되는 것을 특징으로 하는 마이크로프로세서.The microprocessor according to claim 1, wherein said memory register is stored in said storage means on the basis of one of executable instructions. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900001965A 1989-02-17 1990-02-17 Microprocessor KR920006789B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-37805 1989-02-17
JP1037805A JPH0630063B2 (en) 1989-02-17 1989-02-17 Microprocessor

Publications (2)

Publication Number Publication Date
KR900013390A true KR900013390A (en) 1990-09-05
KR920006789B1 KR920006789B1 (en) 1992-08-17

Family

ID=12507729

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900001965A KR920006789B1 (en) 1989-02-17 1990-02-17 Microprocessor

Country Status (5)

Country Link
US (1) US5642523A (en)
EP (1) EP0383342B1 (en)
JP (1) JPH0630063B2 (en)
KR (1) KR920006789B1 (en)
DE (1) DE69028224T2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
JPH07114498A (en) * 1993-10-15 1995-05-02 Toshiba Corp Microprocessor
JP4573189B2 (en) * 1998-10-10 2010-11-04 インターナショナル・ビジネス・マシーンズ・コーポレーション Program code conversion method
JP2000353092A (en) * 1999-06-09 2000-12-19 Nec Corp Information processor and register file switching method for the processor
US6553487B1 (en) * 2000-01-07 2003-04-22 Motorola, Inc. Device and method for performing high-speed low overhead context switch
JP3763518B2 (en) 2001-05-29 2006-04-05 インターナショナル・ビジネス・マシーンズ・コーポレーション COMPILER, COMPILING METHOD THEREOF, AND PROGRAM
EP1470476A4 (en) * 2002-01-31 2007-05-30 Arc Int Configurable data processor with multi-length instruction set architecture
US7127592B2 (en) * 2003-01-08 2006-10-24 Sun Microsystems, Inc. Method and apparatus for dynamically allocating registers in a windowed architecture
JP2006039874A (en) * 2004-07-26 2006-02-09 Fujitsu Ltd Information processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4777588A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance
US5021947A (en) * 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
JP2545789B2 (en) * 1986-04-14 1996-10-23 株式会社日立製作所 Information processing device
JPH0217541A (en) * 1988-07-06 1990-01-22 Hitachi Ltd Stack system micro-computer
US5083263A (en) * 1988-07-28 1992-01-21 Sun Microsystems, Inc. BISC with interconnected register ring and selectively operating portion of the ring as a conventional computer

Also Published As

Publication number Publication date
EP0383342A2 (en) 1990-08-22
JPH02217925A (en) 1990-08-30
JPH0630063B2 (en) 1994-04-20
DE69028224T2 (en) 1997-02-06
US5642523A (en) 1997-06-24
EP0383342A3 (en) 1992-10-07
DE69028224D1 (en) 1996-10-02
EP0383342B1 (en) 1996-08-28
KR920006789B1 (en) 1992-08-17

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