KR940013213A - 역양자화 장치 - Google Patents

역양자화 장치 Download PDF

Info

Publication number
KR940013213A
KR940013213A KR1019920022803A KR920022803A KR940013213A KR 940013213 A KR940013213 A KR 940013213A KR 1019920022803 A KR1019920022803 A KR 1019920022803A KR 920022803 A KR920022803 A KR 920022803A KR 940013213 A KR940013213 A KR 940013213A
Authority
KR
South Korea
Prior art keywords
intra
signal
block
chip select
bkt
Prior art date
Application number
KR1019920022803A
Other languages
English (en)
Other versions
KR0138641B1 (ko
Inventor
김시중
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=19344272&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR940013213(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920022803A priority Critical patent/KR0138641B1/ko
Priority to US08/158,998 priority patent/US5617094A/en
Publication of KR940013213A publication Critical patent/KR940013213A/ko
Application granted granted Critical
Publication of KR0138641B1 publication Critical patent/KR0138641B1/ko
Priority to US09/282,750 priority patent/USRE37568E1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
    • H04N19/107—Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H04N19/126—Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/46—Embedding additional information in the video signal during the compression process
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명은 영상데이타의 처리분야에서 움직임이 있는 영상데이타의 압축방법중 역양자화(Quantization)하는 것으로서 종래의 역양자화 장치는 제어하기가 매우 어렵울 뿐만 아니라 하드웨어의 구성이 매우 복잡하여 생산성이 낮고, 생산비용이 많이 소요되어 제품의 생산원가가 높았다.
본 발명은 3개의 메모리를 구비하고, VLC디코더에서 출력되는 블록 타입신호 및 블록 스트로브신호로 입력데이타가 인트라 DC 또는 AC인지 아니면 난인트라 판별하면서 상기 3개의 메모리에 선택적으로 칩선택신호를 인가하여 QAC 및 QUANT를 저장하고 출력하는 실시간 처리가 가능하고, 제어가 간편하며, 하드웨어의 구성이 단순화되어 제품의 생산성이 향상되고, 생산원가가 절감된다.

Description

역양자화 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 역양자화 장치의 구성을 보인 회로도,
제3도는 제2도의 제어부의 상세 회로도.

Claims (2)

  1. VLC디코더(11)에서 출력되는 QAC 및 QUANT를 각기 저장 및 역 DCT부(12)로 출력하는 인트라 DC메모리(13), 인트라 AC메모리(14) 및 난인트라 DC/AC메모리(15)와, VLC디코더(11)에서 출력되는 블록 타입신호(BKT)및 블록 스트로브신호(BKS)로 인트라 DC 및 AC와 난인트라 모드인지를 판별하여 상기 메모리(13-15)의 칩선택단자(CS1-CS3)에 칩선택신호(IDCS, IADS, NIS)를 선택적으로 출력하는 제어부(16)로 구성함을 특징으로 하는 역양자화 장치.
  2. 제1항에 있어서, 상기에서 제어부(16)는, 블록 타입신호(BKT) 및 블록 스토로브신호(BKS)를 논리합하여 칩선택신호(IDCS)를 출력하는 오아게이트(OR1)와, 인버터(IV1)에서 반전된 블록스트로브신호(BKS)및 블록타입신호(BKT)를 논리합하여 칩선택신호(IACS)를 출력하는 오아게이트(OR2)와, 블록 타입신호(BKT)를 반전시켜 칩선택신호(NIS)로 출력하는 인버터(IV2)로 구성함을 특징으로 하는 역양자화 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920022803A 1992-11-30 1992-11-30 역양자화 장치 KR0138641B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920022803A KR0138641B1 (ko) 1992-11-30 1992-11-30 역양자화 장치
US08/158,998 US5617094A (en) 1992-11-30 1993-11-30 Inverse quantizer
US09/282,750 USRE37568E1 (en) 1992-11-30 1999-03-31 Inverse Quantizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920022803A KR0138641B1 (ko) 1992-11-30 1992-11-30 역양자화 장치

Publications (2)

Publication Number Publication Date
KR940013213A true KR940013213A (ko) 1994-06-25
KR0138641B1 KR0138641B1 (ko) 1998-05-15

Family

ID=19344272

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920022803A KR0138641B1 (ko) 1992-11-30 1992-11-30 역양자화 장치

Country Status (2)

Country Link
US (2) US5617094A (ko)
KR (1) KR0138641B1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0138641B1 (ko) * 1992-11-30 1998-05-15 구자홍 역양자화 장치
DE69721373T2 (de) * 1996-05-14 2004-04-15 Daewoo Electronics Corp. Quantisierer für ein Videokodierungssystem
EP1078532B1 (en) * 1998-05-04 2006-07-19 General Instrument Corporation Method and apparatus for inverse quantization of mpeg-4 video
US6716214B1 (en) * 2003-06-18 2004-04-06 Roger P. Jackson Polyaxial bone screw with spline capture connection
US7091888B1 (en) * 2005-03-29 2006-08-15 Broadcom Corporation Run-level and command split FIFO storage approach in inverse quantization

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU564770B2 (en) * 1981-07-17 1987-08-27 Nippon Electric Co. Ltd. Forward and inverse quantization by varying a reference step size
FR2627926A1 (fr) * 1988-02-29 1989-09-01 Labo Electronique Physique Procede et dispositif de codage de signaux video numeriques, et dispositif de decodage correspondant
KR0138641B1 (ko) * 1992-11-30 1998-05-15 구자홍 역양자화 장치

Also Published As

Publication number Publication date
USRE37568E1 (en) 2002-03-05
US5617094A (en) 1997-04-01
KR0138641B1 (ko) 1998-05-15

Similar Documents

Publication Publication Date Title
KR940013227A (ko) 동화상 복호화 장치
KR960016584A (ko) 화상 디코딩 장치
KR920017479A (ko) 고능률 부호화 장치
KR890017977A (ko) 영상 신호의 방식변환장치
KR940008468A (ko) 편집장치 및 편집신호 디코딩장치
KR910007344A (ko) 영상 신호 처리 장치
KR920020951A (ko) 영상신호 처리장치
KR940010780A (ko) 움직임 보상을 이용한 동영상 신호처리기의 메모리 장치
KR920008660A (ko) 화상표시 제어장치
KR940013213A (ko) 역양자화 장치
KR910015178A (ko) 화상데이터 처리장치
KR950002487A (ko) 비디오 영상을 블럭방향으로 부호화 및 복호화하는 비디오 부호기 및 복호기
KR960005554A (ko) 영상 신호 처리 장치
KR860004349A (ko) 시이퀀스 제어기의 프로세스 입출력장치
JPS6461876A (en) Picture processor
KR950022866A (ko) 양방향 편향 및 디스플레이 장치
KR900015029A (ko) 화상판독장치
KR940012178A (ko) 화상 작성 장치
JPS63228281A (ja) メモリカ−ド
KR920001981A (ko) 뮤즈 디코더의 정지화면 계통 처리회로
JPS6435668A (en) Picture processor
KR920001863A (ko) 이미지 데이타의 복호 및 부호화를 위한 이미지 메모리 억세스 회로
JPS62171276A (ja) 画像デ−タ復号化回路
KR890004251A (ko) 2치 화상 처리에 의한 패턴 식별장치
JPS5760788A (en) Video binary coding system

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091230

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee