KR940012089A - Data output buffer - Google Patents

Data output buffer Download PDF

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Publication number
KR940012089A
KR940012089A KR1019920022632A KR920022632A KR940012089A KR 940012089 A KR940012089 A KR 940012089A KR 1019920022632 A KR1019920022632 A KR 1019920022632A KR 920022632 A KR920022632 A KR 920022632A KR 940012089 A KR940012089 A KR 940012089A
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South Korea
Prior art keywords
pull
voltage
output
output buffer
data output
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KR1019920022632A
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Korean (ko)
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KR950000533B1 (en
Inventor
황홍선
배명호
전동수
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김광호
삼성전자 주식회사
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Priority to KR1019920022632A priority Critical patent/KR950000533B1/en
Publication of KR940012089A publication Critical patent/KR940012089A/en
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Publication of KR950000533B1 publication Critical patent/KR950000533B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 반도체 메모리장치, 특히 데이타 출력버퍼에 관한 것으로, 출력버퍼를 형성하는 출력구동단의 풀업및 풀다운 모오스트랜지스터의 게이트막에 고전계가 인가되어 게이트내압이 나빠져서 소자의 신뢰성이 떨어지는 문제점을 개선하기 위하여, 외부전압을 정형하여 소정크기의 내부 전원전압을 발생시키는 내부전압 발생회로와,데이타 출력 인에이블신호에 액티브되며 메모리소자 내부의 출력을 받아 상기 출력구동단의 풀업 및 풀다운 트랜지스터를 내부전원전압의 레벨로 상보적으로 턴온시키는 출력구동단 제어회로를 구비하여, 상기 풀업 및 풀다운 트랜지스터의 게이트 단자에 인가되는 전압이 출력될 데디타의 크기에 따라 능동적으로 대응하여 인가되도록 하여 상기 트랜지스터들의 게이트막을 보호하는 데이타 출력버퍼를 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a data output buffer, in which a high electric field is applied to a gate film of a pull-up and pull-down MOS transistor of an output driving stage forming an output buffer, thereby reducing the gate breakdown voltage, thereby reducing reliability of the device. To this end, an internal voltage generation circuit for generating an internal power supply voltage of a predetermined size by shaping an external voltage and a data output enable signal are activated and receive an output from a memory device to supply the pull-up and pull-down transistors of the output drive stage with an internal power supply voltage. An output driving stage control circuit which turns on complementarily to a level of?, So that a voltage applied to the gate terminals of the pull-up and pull-down transistors is actively applied correspondingly according to the size of the data to be output. Provide a data output buffer to protect .

Description

데이타 출력버퍼Data output buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 데이타 출력버퍼,2 is a data output buffer according to the present invention,

제3도는 각2도의 각 노드의 전압크기를 나타내는 전압특성도,3 is a voltage characteristic diagram showing the voltage magnitude of each node of each 2 degrees,

제4도는 제2도에 따른 구제회로도.4 is a relief circuit according to FIG.

Claims (3)

외부전원과 출력노드사이에 접속된 풀업 트랜지스터와 상기 출력노드의 접지전압사이에 접속된 풀다운 트랜지스터로 이루어진 출력구동단과, 데이타 출력 인에이블신호에 의해 액티브되며 메모리소자 내부의 출력을 받아 상기 출력구동단의 풀업 및 풀다운 트랜지스터를 상보적으로 턴온시키는 출력구동단 제어회로와, 상기 외부전원을 정형하여 일정크기의 내부전압을 발생시켜 상기 출력구동단 제어회로의 동작전압으로 공급하는 내부전압 발생회로를 구비하며 반도체 메모리소자의 출력단에 접속되어 소자외부로 데이타를 출력하는 제이터 출력버퍼에 있어서, 상기 풀업 및 풀다운 트랜지스터의 게이트단자에 인가되는 전압이 외부전원전압의 크기에 능동적으로 대응하여 인가되도록 하여 상기 트랜지스터들의 게이트막을 보호함을 특징으로 하는 반도체 메모리장치의 데이타 출력 버퍼.An output driving stage consisting of a pull-up transistor connected between an external power supply and an output node and a pull-down transistor connected between a ground voltage of the output node, and activated by a data output enable signal and receiving an output of a memory device. An output drive stage control circuit for complementarily turning on the pull-up and pull-down transistors; and an internal voltage generation circuit configured to generate an internal voltage of a predetermined size by supplying the external power supply to an operating voltage of the output drive stage control circuit. And a jitter output buffer connected to an output terminal of the semiconductor memory device and outputting data to the outside of the device, wherein a voltage applied to a gate terminal of the pull-up and pull-down transistors is actively applied corresponding to the magnitude of an external power supply voltage. To protect the gate film of the transistors The data output buffer of the semiconductor memory devices. 제1항에 있어서, 상기 풀업 트랜지스터와 풀다운 트랜지스터는 각각 직렬 접속된 제1, 제2엔모오스트랜지스터 및 제3, 제4엔모오스 트랜지스터로 구성됨을 특징으로 하는 반도체 메모리장치의 데이타 출력버퍼.2. The data output buffer of a semiconductor memory device according to claim 1, wherein the pull-up transistor and the pull-down transistor are respectively composed of first, second and fourth enMOS transistors connected in series. 제2항에 있어서, 상기 데이타 출력버퍼가 “하이”를 출력할때에는 제1, 제2엔모오스 트랜지스터의 게이트단자에는 상기 내부전압과 높은 전압을 인가하고 제3, 제4엔모오스 트랜지스터의 게이트단자에는 각각 내부전압 및 접지전압을 인가하며, 상기 데이타 출력버퍼가 “로우”를 출력할때에는 제1, 제1엔모오스 트랜지스터의 게이트단자는 각각 내부전압 및 접지전압을 인가하고 제3, 제4엔모오스 트랜지스터의 게이트단자에는 각각 내부전압을 인가함을 특징으로 하는 반도체 메모리장치의 데이타 출력버퍼.The gate terminal of the third and fourth NMOS transistors according to claim 2, wherein the internal and high voltages are applied to the gate terminals of the first and second NMOS transistors when the data output buffer outputs "high." Internal voltage and ground voltage are respectively applied to the gate, and when the data output buffer outputs "low", the gate terminals of the first and first NMOS transistors respectively apply an internal voltage and a ground voltage. A data output buffer of a semiconductor memory device, characterized in that an internal voltage is applied to each gate terminal of a MOS transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920022632A 1992-11-27 1992-11-27 Data output buffer KR950000533B1 (en)

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KR1019920022632A KR950000533B1 (en) 1992-11-27 1992-11-27 Data output buffer

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KR950000533B1 KR950000533B1 (en) 1995-01-24

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422821B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Output buffer
KR100643912B1 (en) * 2004-11-03 2006-11-10 매그나칩 반도체 유한회사 Data output buffer
KR101677887B1 (en) * 2015-07-07 2016-11-21 (주)에이디테크놀로지 Buffer for Bidirectional Common Bus and Bus Circuit Comprising the Buffers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422821B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Output buffer
KR100643912B1 (en) * 2004-11-03 2006-11-10 매그나칩 반도체 유한회사 Data output buffer
KR101677887B1 (en) * 2015-07-07 2016-11-21 (주)에이디테크놀로지 Buffer for Bidirectional Common Bus and Bus Circuit Comprising the Buffers

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Publication number Publication date
KR950000533B1 (en) 1995-01-24

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