KR940010793A

KR940010793A - Input data control circuit of motion estimation processing

Info

Publication number: KR940010793A
Application number: KR1019920020026A
Authority: KR
Inventors: 이순건
Original assignee: 윤종용; 삼성전자 주식회사
Priority date: 1992-10-29
Filing date: 1992-10-29
Publication date: 1994-05-26
Also published as: KR0178890B1

Abstract

입력데이타 제어부에서 current-data SW-UL, SW-UR, SW-LL, SW-LR 데이타를 시작(START) 신호에 의해서 받아 이를 데이타 선택신호에 의해서 출력하고, 상기 입력데이타 제어부(101)로부터 PE(-8, -8), …PE (7, 7)에 입력되는 데이타 X(-8, -8), Y(-8, -8) , … X(7, 7), Y(7, 7)를 받아들여 블럭 매치 알고리즘 처리부(102)에서 현재 블럭과 탐색창내 256개의 독립블럭과의 블럭 정합 연산을 수행한다.The input data controller receives the current-data SW-UL, SW-UR, SW-LL, and SW-LR data by the START signal and outputs the data by the data selection signal, and sends the PE from the input data controller 101. (-8, -8),... Data X (-8, -8), Y (-8, -8),... Input to PE (7, 7); The block match algorithm processing unit 102 accepts X (7, 7) and Y (7, 7) and performs a block matching operation between the current block and 256 independent blocks in the search window.

그리고, 상기 블럭 매치 알고리즘 처리부(102)에서 구해진 각 블럭별에러신호 D(i, j)-(8≤, j≤7)를 받아들여 그중에서 가장 값이 적은 블럭을 찾아내어 최소 절대치 에러부(103)에서 그때의 움직임 벡터 및 에러값(zoffset-MSB, zoffset-LSB)를 8비트를 버스를 통해 절대화를 취한 최소값을 출력한다.Then, the block match algorithm processing unit 102 receives the error signals D (i, j)-(8≤, j≤7) for each block, finds the smallest block among them, and finds the least absolute error unit ( In 103), the minimum value obtained by absoluteizing the motion vector and the error values (zoffset-MSB and zoffset-LSB) by 8 bits through the bus is output.

Description

Input data control circuit of motion estimation processing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 블럭도,1 is a block diagram according to the present invention,

제2도는 본 발명에 따른 블럭, 탐색 윈도우 관계도,2 is a block and search window relation diagram according to the present invention;

제3도는 제1도의 입력데이타 제어부(101)의 구체회로도.3 is a detailed circuit diagram of the input data control unit 101 of FIG.

Claims

In the signal compression circuit of the image processing apparatus, an input data control unit which receives current-data, SW-UL, SW-UR, SW-LL, and SW-LR data as a START signal and outputs it as a data selection signal. (10) and PE (-8, -8),... From the input data control unit 101. , Data X (-8, -8), Y (-8, -8) input to PE (7, 7),... A block match algorithm processing unit 102 that accepts X (7, 7) and Y (7, 7) and performs a block matching operation between the current block and 256 independent blocks in the search window, and the block match algorithm processing unit 102 ) Receives the error signals D (i, j)-(8≤, j≤7) for each block, and finds the block with the lowest value among them. Then, the motion vector and the error value (zoffset-MSB, zoffset- And an LSB) comprising a minimum absolute error section 103 for outputting 8 bits through a bus.

The first and second means according to claim 1, wherein the input data control unit 101 delays the input data every clock to provide and transmit the input data to each processing element of the n matching blocks. Second means for generating a signal, third means for inputting data for the upper and lower search window pixels, and left, right, and top of the third means according to the search window selection control signal of the second means. Fourth means for selectively outputting the lower search window pixel data, fifth means for generating a clear signal every predetermined period to generate a search selection control signal of the second means, and a counting signal for the fifth means; And an input data control circuit for motion estimation processing, characterized by comprising sixth means.

※ Note: The disclosure is based on the initial application.