KR940010670B1 - Subtractor - Google Patents

Abstract

The device does not need a adder, and reduces the area of layout by a regularity in cells. The device includes a borrow generation and transmission circuit which outputs the signals; 1st to 16th, a borrow generater which has a 1st inverter, a 1st CMOS transmission gate, a 1st NMOS transmission gate, a borrow transmission circuit which has a 2nd inverter, a 2nd CMOS transmission gate, a 2nd NMOS transmission gate, a 1st cell which has a 1st AND gate, an OR gate, a 2nd AND, a 3rd cell which has the 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th PMOS and NMOS transistors, and a 2nd cell which has a 4th inverter and a subtractor.

Description

Subtractor

1 shows a block diagram of a conventional n-bit parallel subtractor.

2 shows a block diagram of an n-bit parallel subtractor according to the present invention.

3 shows a specific circuit configuration of the 24-bit parallel subtractor of the embodiment according to the present invention.

Figure 4a shows an embodiment of a bore generating circuit according to the present invention.

Figure 4b shows an embodiment of the bowl transmission circuit according to the present invention.

4c illustrates an embodiment of a first cell block according to the present invention.

4d illustrates an embodiment of a second cell block according to the present invention.

4e illustrates an embodiment of a third cell block according to the present invention.

4F illustrates an embodiment of a fourth cell block according to the present invention.

5 shows a tree structure of the borough evaluation block according to the present invention.

6 shows a simulation result of a subtractor according to the present invention.

The present invention relates to a subtractor, in particular to a parallel subtractor.

The algorithm of the conventional n-bit parallel subtractor is as follows. Invert the subtracted B by n inverters for n bits of word A and B, and inverted B into n + 1 bits by extending the sign bit of A by 1 bit, and then carry it with the carry input signal. Subtraction was performed by adding with an n + 1 bit adder.

A-B = A + (2's complement of B)

= A + ( +1)

= D

1 shows a block diagram of a conventional parallel subtractor for performing the above algorithm.

The method of claim 1, also, the inverted and supervision (B _i, i = 1,2, ..., n) of the inverters, which inverts the input (1), the minuend (A _i, i = 1,2, ..., n) It consists of an n + 1 bit adder 2 which inputs and adds a subtraction (B _i , i = 1, 2, ..., n) and a carry signal (C _in = 1). Therefore, an adder of n + l bits has always been necessary to perform subtraction of n bits. In other words, in order to perform the subtraction, it is necessary to invert the subtracted and perform the addition of n + l bits. Therefore, the conventional method has a disadvantage in that the circuit configuration is complicated and the speed of performing the subtraction is slow.

An object of the present invention is to provide a subtractor with a simple circuit configuration.

Another object of the present invention is to provide a subtractor having a high speed of performing subtraction.

In order to achieve the above object, the subtractor of the present invention inputs 16 bit first and second data signals, and b _i = B _i , p _i = A _i ⊙B _i (where b _i is a bore generation signal, p _i is a bore transmission signal, A _i is a first data signal, B _i is a second data signal, i = 1,... And 16, respectively, to generate the first to sixteenth generation of the bow generation and the transmission output signals, and the third generation, the third generation, the fourth generation of the generation and transmission circuits. 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 Bore generation and transmission output signals are respectively inputted, and NB = b _i ∪ (p _i ∪b _{i 1} ), NP = p _i ∪p _i-1 (where NB is the Borrow generation output signal of the first cell and NP is the Borrow transmission output signal of the first cell, respectively). NB = b _i ∪ (b _i-1 ∪p _i) by inputting the first first cells that output the bore generation and transmission output signals, and the first and second bore generation and transmission output signals of the bore generation and transmission circuits. (Where NB is The first and second cells outputting the Borrow generation output signal by performing the operation of the formula, and the Borrow output signal of the first and second cells, and the Borrow generation and transmission circuit. NB = b _i ∪ (b _i-1 ∪p _i ) (wherein, NB is a third input by inputting a _third bore generation and transmission output signal, a _first bore generation and transmission output signal of the first first cells, respectively) The second second cells for outputting the borough generation output signals by performing an operation of the formula 2) and the second bore generation and transmission output signal of the first first cells, and the Inputs a seventh bore generation and transmission output signal, a third bore generation and transmission output signal of the first cells, and generates a fourth bore generation and transmission output of the first cells; Signal and the bore generation And inputting an eleventh borough generation and a transmission output signal of the transmission circuit, a fifth bore generation and a transmission output signal of the first first cells, respectively, and a sixth bore generation and a transmission output signal of the first first cells; The borough generation and the fifteenth borough generation and transmission output signal of the transmission circuit, the seventh borough generation and transmission output signal of the first first cells are respectively inputted, and NB = b _i ∪ (b _i ∪b _i-1 ). , NP = p _i ∪p _i-1 (where NB is the bore generation output signal of the first cell and NP is the bore transmission output signal of the first cell, respectively). Second first cells for outputting transmission output signals, second bore output signals of the second second cells and the fifth bore generation and transmission output signals of the bore generation and transmission circuits, the first first cell Of the second bore generation and transmission output signal, the second Inputting the first and second borough generation and transmission output signals of one cell, respectively, a fourth borrow generation and transmission output signal of the second first cells, and the thirteenth generation and transmission output signal of the borrow generation and transmission circuit, Inputs the sixth bore generation and transmission output signal of the first first cells, the fifth bore generation and transmission output signal of the second first cells and inputs NB = b _i ∩ (p _i ∪b _i-1 ). , NP = p _i ∪p _i-1 (where NB is the bore generation output signal of the first cell and NP is the bore transmission output signal of the first cell, respectively). Third first cells for outputting transmission output signals, second bore output signals of the second second cells and the fifth bore generation and transmission output signals of the bore generation and transmission circuits, the first first cell Second bore generation and transmission output signal, the second first cell Of the expression of the operation of the first Harborough generate and transmit an output signal to each of the input _{NB = b i ∩ (b i} -1 ∪p i) ( here, NB means the Harborough generating an output signal of the second cell.) Third second cells that perform output of the borough generation output signals; first, second, second, fourth, and sixth boring generation and transmission output signals of the second first cells and second bores of the second second cells; Input the output signal c _{i + 1} = b _i ∩ (p _i ∪b _i-1 ) ∩ (p _i ∪p _i-1 ∪p _i-2 ) ∩ (p _i ∪p _i-1 ∪p _{i- 2} ∪p _i-3 ) (where c _{i + 1} refers to the carry output signal of the third cell); The fourth bore output signal of the third second cells and the ninth bore generation and transmission output signal of the bore generation and transmission circuit, the fourth bore generation and transmission output signal of the first first cells, the second NB = b _i ∩ (b _i-1) by inputting the third and fourth borough generation and transmission output signals of the first cells of the first cell and the first, second and third borough generation and transmission output signals of the third first cells, respectively. Ip _i ) (fourth second cells outputting a bore generation and transmission output signals, and performing a calculation of the formula of NB here). The final difference value for outputting the final difference value by inputting the first bore generation and transmission output signal of the transmission circuit, the bore generation output signals of the second cells of the first, second, third, and fourth cells, and the carry output signals of the third cell. A calculation circuit is provided.

The algorithm will be described before explaining the subtractor according to the present invention with reference to the accompanying drawings.

General binary subtraction is represented by the following truth table:

Deriving a Boolean expression satisfying the truth table is as follows.

D _i = x _i y _i z _i

= x _i ⊙y _i ⊙z _i

B _i = y _i + (x _i + y _i ) z _i

= y _i + (x _i ⊙ y _i ) z _i

Where, operator " "Is defined as follows.

(b, p) (b ', p') = (b + pb ', pp')

Block boring occurrence and transmission signals B _i , P _i

(B _i , P _i ) = (b _i , p _i ) (B _i-1 , p _i-1 )

= (b _i , p _i ) (b _i-1 , p _i-1 )... (b ₁ , p ₁ )

And the final output D _i is

D _i = p _i B _i-1

to be.

Where b _i = y _i ; Borrow occurrence

p _i = x _i ⊙ y _i ; Borough transmission

2 shows a block diagram of the present invention for performing the algorithm.

2, a bow generation and transmission block (3) for generating a bow generation and a transmission signal (b _i , p _i ) by inputting the subtracted (A _i ) and the subtraction (B _i ); It consists of a bow evaluation block 4 which inputs the output signal of (3), and evaluates a bow, and the difference block 5 which inputs the output signal of the said bow evaluation block 4. As shown in FIG.

FIG. 3 shows the structure of the 24-bit subtractor of the specific embodiment of the block diagram shown in FIG.

In FIG. 3, two 24-bit numbers (A ₂₃ -A ₀ , B ₂₃ -B ₀ ) are inputted to indicate a 24-bit bore generation signal (b ₂₃ -b ₀ ) and a transmission signal (p ₂₃ -p ₀ ). Borrow generation and transmission circuit (10 ₂₃ -10 ₀ ), which performs the following operations that generate

b _i = B _i

p _i -A _i ⊙ B _i

By entering the Harborough generate and transmit signals, the first cell block to perform the following operations (11 ₂₃ -11 ₀ 12 ₁₁ -12 _2, 13 _{6-13 4),}

NB = b _i ∩ (p _i ∪b _i-1 )

NP = p _i ∪p _i-1

Second cell blocks 11 ₀ , 12 ₁ , 12 ₀ , 13 ₃ -13 ₀ , 13 ₁₀ -13 ₇ , 15 ₁₄ -15 ₀ , which perform the following operation by inputting the borough generation and the transmission signal,

NB = b _i ∩ (b _i-1 ∪p _i )

Borrow generation and transmission signals (b _i , p _i ), (b _i-1 , p _i-1 ), (b _i-2 , p _i-2 ), (b _i-3 , p _i-3 ) A third cell block 14 which inputs to perform the next operation,

C _{i + 1} = b _i ∩ (p _i ∪b _i-1 ) ∩ (p _i ∪p _i-1 ∪p _i-2 ) ∩ (p _i ∪p _i-1 ∪p _i-2 ∪p _{i- 3} )

It consists of a subtraction block (16 ₀ -16 ₂₂₎ to enter the Harborough generation signal and the transmission signal output a difference signal (D ₀ -D _22).

The operation according to the above configuration is as follows.

The Harborough the generation and transmission in step 1, the circuit (10 ₀ -10 ₂₃₎ is Harborough generation signal _{(b i, i = 23,} 22, ..., 0) and transmission signals (pi, i = 23, 22 , ..., 0 Will occur).

The second cell blocks (11 ₀₎ is performing an operation to enter the first of two output signals (b _1, p _1, b ₀₎ of the Harborough generation and transmission circuit and said first cell block (11 in step 2, ₁ -11 ₁₁₎ is to operate with two pairs of input output signals _{(b i, p i, i} = 2, 3, ..., 23) of the Harborough generation and transmission circuitry.

A second cell block at the third stage (12 ₀₎ is performing an operation to input an output signal of the output signals and the carry generation and transmission circuit (10 ₂₎ of the second cell blocks (11 ₀₎ and the second cell The block 12 ₁ performs an operation by inputting an output signal of the first cell block 11 ₁ and an output signal of the second cell block 11 ₀ , and performs operation on the first cell blocks 12 ₃ , 12 ₅ ,. 12 ₇ , 12 ₉ , and 12 ₁₁ input two pairs of output signals of the first cell blocks ₁₁ 11-11 ₂ to perform arithmetic operations. The first cell blocks 12 ₂ , 12 ₄ , 12 ₆ , 12 ₈ and 12 ₁₀ denote an output signal of the first cell blocks 11 ₂ , 11 ₄ , 11 ₆ , 11 ₈ , 11 ₁₀ , and the bore generation and transmission circuits 10 ₆ , 10 ₁₀ , 10 ₁₄ , 10. ₁₈ , 10 ₂₂ ) to input the output signals, respectively.

The cells in the second block from step 4 (13 ₀ -13 _3), the second cell block (12 ₁₎ and the output signal Harborough generation and transmission circuit (10 ₄₎ output signal, the first cell of the block (11 ₂₎ an output signal, wherein in the first cell block (performs an operation to respectively input the output signals of the 12 _2, 12 ₃₎ and the first cell block (13 ₁₀ -13 ₇₎ of said first cell block (12 ₉ ), the output signal of the borough generation and transmission circuit 10 ₂₀ , and the output signal of the first cell blocks 11 ₁₀ , 12 ₁₁ , 12 ₁₀ are input to perform an operation, and the second cell the block (13 _6, 13 _5, 13 ₄₎ is the first cell block (12, ₅₎ the output signal and the Harborough generation of and transmission circuit (10, _12), the first cell block (11 _6, 12 ₆₎ The third cell block 14 inputs an output signal of the second cell 12 ₁ and an output signal of the first cells 12 ₃ , 12 ₅ , and 12 ₇ . Perform the operation.

The second cell block in the fifth step (15 ₆ -12 ₀₎ of the second cell block output signal and the Harborough generation and transmission circuit (10 _8), the first cell block (13 _3, 11 _4, 12 _4, 12 _5, 13 _4, 13 _5, 13 ₆ s) the output signal to perform an operation, and second cell blocks (15 ₁₄ -15 ₇₎ the Harborough generating and transmitting circuits (10 _16), the The operation is performed by inputting output signals of the first cell blocks 12 ₈ , 12 ₉ , and 13 ₇ -13 ₁₀ , respectively.

In a sixth phase difference circuit (16 ₀₎ and generates a sum signal (S ₁₎ to the output signal of the output signal and the second cell blocks (11 ₀₎ of said Harborough generation and transmission circuit (10 ^±), difference circuit (16 ₁₎ is the second cell blocks (11 ₀₎ and the output signal of the Harborough generation and transmission circuit (10 ₂₎ to generate a difference signal (D _2), and the secondary circuit (16 ₂₎ The difference signal D ₃ is inputted by inputting the output signal of the bore generation and transmission circuit 10 ₃ and the second cell block 12 ₀ , and the difference circuit 16 ₃ receives the bore generation and transmission circuit ( 10 ₄₎ and the second output a cell block (12 ₁₎ the difference signal (D ₄₎ to input the output signal of, and difference circuit (16 ₇ -16 ₄₎ is the Harborough generation and transmission circuit (10 ₈ -10 ₅₎ the output signal and the second cell blocks (13 ₀ -13 _3), each input to a difference signal (D ₈ -D _5), the output, and the difference circuit (16 ₁₄ -16 _8), the output signals of the said Harborough Generation and transmission circuits (10 ₁₅ -10 ₉₎ output signals and said second cells (15 ₆ -15 _0), and each type of output signal and output a difference signal (D ₁₅ -D _9), primary circuit (16, ₁₅ a of) the above Harborough the input and generating an output signal of the transmission circuit (10, ₁₆₎ the output signal of the third cell block 14 of the output a difference signal (D _16), and the secondary circuit (16 ₂₂ -16 _17), and generating the Harborough transfer circuit (10 ₂₃ -10 ₁₇₎ of said second cell block and the output signals (15 ₁₃ -15 ₇₎ the output signals respectively input to the output of the difference signal (D ₂₂ -D _17), and the primary circuit of the An input unit 16 ₂₃ outputs the difference signal D ₂₄ by inputting the output signal of the bore generation and transmission circuit D ₂₃ and the output signal of the second cell block 15 ₁₄ . Here, the difference circuit 16 ₂₃ is a block added to process the sign bit when there is a sign bit. If there is no sign bit, it may be added.

FIG. 4A shows the bore generating circuit of the bore generating block shown in FIG.

The 4a also in the input signal (B _i) a response to the inverter 25, the input signal (B _i) and the inverted input signal (B _i) for reversal for outputting an input signal (A _i) in CMOS transfer gate 26 and an NMOS transfer gate 27 for transmitting an inverted input signal _Bi in response to the input signal _Bi . Thus, when the input signal A _i is at the "low" level and the input signal _Bi is the "high" level signal, a signal of the "high" level is output.

FIG. 4B shows the circuit of the borough transmission block shown in FIG.

The 4b FIG, CMOS transmission for transmitting the input signal inverter 30, the input signal (B _i) and the inverted input signal (B _i) input signals in response to (A _i) for inverting the (Bi) in gate 31, the input signal (a _i) in response to an input signal (B _i), the NMOS transfer gate 32, and the input signal (a _i) in response to an inverted input signal (B _i in order to transmit It is composed of a PMOS transfer gate 33 for transmitting the. Therefore, when the signal level of the input signal A _i and the input signal _Bi is the same, the signal of the "high" level is output. That is, the operation of EXNOR is performed.

4C shows the circuit of the first cell of the borough evaluation block.

In FIG. 4C, an AND gate 40 for performing an AND operation on the borough transmission signal _pi and the borough generation signal b _i-1 , an output of the borough generation signal b _i , and the AND gate 40 is shown. OR gate 41 for ORing the signal, and AND gate 42 for ANDing the carry transmission signals _pi and _pi-1 . That is, the output signal NB and the output signal NP perform the following logic equation.

NB = b _i + (p _{ib i-1} )

_{NP = p i · p i-} 1

4d shows the circuit of the second cell of the borough evaluation block.

4d is composed of a gate 50 and an OR gate 51 for generating an output signal NB in the circuit of FIG.

4E shows the circuit of the third cell of the borough evaluation block.

In FIG. 4E, the gate connection signals are connected in series between the power supply voltage V _DD and the ground voltage V _SS , and the bore generation signals b _i , b _i-1 , b _i-2 , and b _i-3 are respectively gated. Four PMOS transistors 60, 61, 62, and 63 input to the electrode, four NMOS transistors 64, 65, 66, and 67, a gate electrode connected to the gate electrode of the PMOS transistor 60, and the PMOS transistor An NMOS transistor 71 having a drain electrode connected to the drain electrode of (63) and a source electrode connected to a ground voltage, a source electrode connected to the drain electrode of the PMOS transistor 63 and the source electrode of the NMOS transistor 66; An NMOS transistor 73 having a NMOS transistor 72, a drain electrode of the PMOS transistor 63, a drain electrode connected to the drain electrode of the NMOS transistor 65, and a borough transfer signal _pi are input to the gate electrode. The drain electrode of the PMOS transistor 60 and The PMOS transistor 68 having a source electrode and a drain electrode respectively connected to the drain electrode of the PMOS transistor 63, the borough transfer signal p _i-1 are input to the gate electrode, and the drain electrode of the PMOS transistor 61 is connected to the drain electrode. A PMOS transistor 69 having a source electrode and a drain electrode connected to the drain electrode of the PMOS transistor 63 and a carry transfer signal p _i-2 are input to a gate electrode, and the drain electrode and the PMOS of the PMOS transistor 62 are input. NMOS transistor 64 having a PMOS transistor 70 connected to the drain electrode of the transistor 63 and a gate electrode connected to the gate electrode of the PMOS transistor 63.

4f shows the circuit of the difference block according to the invention.

The 4f Fig, NMOS transistor for transmitting the Harborough transmission signal (p _i), the inverter (75), in response to the output signal (b _i) of the Harborough evaluation block the Harborough transmission signal (p _i) for inverting the on ( 76), the PMOS transistor 77 which transmits the output signal of the inverter 75 in response to the inverted output signal b _i of the bore evaluation block, and the bore transmission signal b in response to the output signal _pi . _i ) and a CMOS transfer gate 78 for transmitting the difference signal D _i .

5 shows a tree structure of a borough evaluation block of a 24-bit subtractor according to the present invention.

6 shows a simulation result of a 24-bit subtractor according to the present invention.

The polyoperator in the tree structure is a function that calculates a new b _i ', p _i ' from four b _i and p _i .

In the case where n = 16, the present invention can be calculated in only four steps as compared to the prior art.

In addition, in the case of n = 16, if the expansion shown in Fig. 3 is expanded to increase by one step every multiple of 16, it is possible to construct an adder having a much lower transmission delay than an adder made by the prior art. .

In the above embodiment, only a 16-bit tree structure is shown, but each 16-bit increment increases the tree structure. That is, when 32 bits are used, two tree structures are required, and the tree level is increased by one.

Therefore, the present invention, firstly, does not require an addition circuit for subtraction.

Second, since the cells have regularity, the layout is easy at the time of layout, and the area is reduced.

Claims (7)

Bore generation and transmission circuits for inputting 16-bit first and second data signals to perform the following equations and outputting the first to sixteenth generation and transmission output signals; b _i = B _i p _i = A _i ⊙ B _i (B _i denotes a borough generation signal, p _i denotes a borough transmission signal, A _i denotes a first data signal, and B _i denotes a second data signal, i = l, ..., 16, respectively.) The bore generation and transmission output signals of the third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelve, thirteenth, fourteenth, and fifteenth and sixteenth transmission circuits First first cells for inputting and performing the operation of the following expressions to output the Borrow generation and transmission output signals; NB = b _i ∪ (p _i ∩b _i-1 ) NP = p _i ∩p _i-1 (In this case, NB denotes a bore generation output signal of the first cell, and NP denotes a bore transmission output signal of the first cell, respectively.) A first second cell for inputting the bore generation and transmission output signals of the first and second generation of the bore generation and transmission circuits and performing a calculation as follows; NB = b _i ∪ (b _i-1 ∩p _i ) (NB here refers to the bore generation output signal of the second cell.) The Borough output signal of the first second cell, the Borough generation and the third bore generation and the transmission output signal of the transmission circuit and the first Bore generation and the transmission output signal of the first cells are respectively inputted below. Second second cells configured to perform arithmetic operation to output the borough generation output signals; NB = b _i ∪ (b _i-1 ∩p _i ) (NB here refers to the bore generation output signal of the second cell.) A second bore generation and transmission output signal of the first first cells, a seventh bore generation and transmission output signal of the bore generation and transmission circuit, a third bore generation and transmission output signal of the first first cells A fourth bore generation and transmission output signal of the first first cells and an eleventh bore generation and transmission output signal of the bore generation and transmission circuit, a fifth bore generation and transmission output of the first first cells, respectively; A sixth bore generation and a transmission output signal of the first first cells and a fifteenth bore generation and a transmission output signal of the first and second circuits, and a seventh bore generation of the first cells; And second first cells for inputting a transmission output signal, respectively, and performing a calculation of the following expression to generate a borough generation and transmission output signals; NB = b _i ∪ (p _i ∩b _i-1 ) NP = p _i ∩p _i-1 (In this case, NB denotes a bore generation output signal of the first cell, and NP denotes a bore transmission output signal of the first cell, respectively.) The second bore output signal of the second second cells and the fifth bore generation and transmission output signal of the bore generation and transmission circuit, the second bore generation and transmission output signal of the first first cells, the second Inputting the first and second borough generation and transmission output signals of the first cells of the fourth cell and the fourth and second borough generation and transmission output signals of the second first cells, and the thirteenth generation and transmission output signal of the borough generation and transmission circuit. Inputs a sixth bore generation and transmission output signal of the first first cells, a fifth bore generation and transmission output signal of the second first cells, and performs the following equation to generate the bow generation and transmission output. Third first cells for outputting signals; NB = b _i ∪ (p _i ∩b _i-1 ) NP = p _i ∩p _i-1 (In this case, NB denotes a bore generation output signal of the first cell, and NP denotes a bore transmission output signal of the first cell, respectively.) The second bore output signal of the second second cells and the fifth bore generation and transmission output signal of the bore generation and transmission circuit, the second bore generation and transmission output signal of the first first cells, the second Third second cells configured to input first borough generation and transmission output signals of the first cells of the cell and output the borough generation output signals by performing the following equation; NB = b _i ∪ (b _i-1 ∩p _i ) (NB here refers to the bore generation output signal of the second cell.) Carry output signal by inputting the first, second, four, six borough generation and transmission output signals of the second first cells and the second borough output signal of the second second cells to perform the following equation A third cell generating a; C _{i + 1} = b _i ∩ (p _i ∪b _i-1 ) ∩ (p _i ∪p _i-1 ∪p _i-2 ) ∩ (p _i ∪p _i-1 ∪p _i-2 ∪b _{i- 3} ) (Here, c _{i + 1} refers to the carry output signal of the third cell.) The fourth bore output signal of the third second cells and the ninth bore generation and transmission output signal of the bore generation and transmission circuit, the fourth bore generation and transmission output signal of the first first cells, the second Generates the third and fourth borough generation and transmission output signals of the first cells of the first cell, and the first, second and third borough generation and transmission output signals of the third first cells, respectively, and performs the following equation. And fourth second cells for outputting transmission output signals; And NB = b _i ∪ (b _i-1 ∩p _i ) (NB here refers to the bore generation output signal of the second cell.) The first difference generation and transmission output signal of the generation and transmission circuits, the occurrence generation signals of the second cells of the first, second, third, and fourth cells, and the carry output signals of the third cell are inputted to obtain a final difference value. And a final difference value calculating circuit for outputting. 2. The apparatus of claim 1, wherein the bore generating circuit comprises: a first inverter for inverting the second data signal; A first CMOS transfer gate for outputting the first data signal in response to the second data signal inverted with the second data signal, for transmitting the second data signal inverted in response to the second data signal And a first NMOS transfer gate. 2. The second inverter of claim 1, wherein the bore transmission circuit comprises: a second inverter for inverting the second data signal; a second CMOS for transmitting the first data signal in response to the second data signal inverted with the second data signal; A transfer gate, a second NMOS transfer gate for transmitting the second data signal in response to the first data signal; And a first PMOS transfer gate for transmitting the second data signal inverted in response to the first data signal. 2. The apparatus of claim 1, wherein the first cell comprises: a first AND gate for ANDing the first bore transmission signal and the first bore generation signal; An OR gate for ORing the second bore generation signal and the output signal of the first AND gate; And a second AND gate configured to logically multiply the first and second Borough transmission signals. 2. The second PMOS transistor of claim 1, wherein the third cell includes a source electrode connected to a power supply voltage and a gate electrode for inputting a first bore generation signal, and a source electrode and a second bore connected to the drain electrode of the second PMOS transistor. A third PMOS transistor having a gate electrode for inputting a signal; A fourth PMOS transistor having a source electrode connected to the drain electrode of the third PMOS transistor and a gate electrode for inputting a third bore generation signal; A fifth PMOS transistor having a source electrode connected to the drain electrode of the fourth PMOS transistor and a gate electrode for inputting a fourth borough generation signal; A third NMOS transistor having a drain electrode connected to the drain electrode of the fifth PMOS transistor and a gate electrode for inputting the fourth borough generation signal; A fourth NMOS transistor having a drain electrode connected to the source electrode of the third NMOS transistor and a gate electrode for inputting a first borough transmission signal; A fifth NMOS transistor having a drain electrode connected to the source electrode of the fourth NMOS transistor and a gate electrode for inputting a second borough transmission signal; A sixth NMOS transistor having a drain electrode connected to a source electrode of the fifth NMOS transistor, a gate electrode for inputting a third borough transmission signal, and a source electrode connected to a ground voltage; A sixth PMOS transistor having a source electrode connected to the drain electrode of the second PMOS transistor, a gate electrode for inputting the third borough transmission signal, and a drain electrode connected to the drain electrode of the fifth PMOS transistor; A seventh PMOS transistor having a source electrode connected to the drain electrode of the third PMOS transistor, a gate electrode for inputting the second borough transmission signal, and a drain electrode connected to the drain electrode of the fifth PMOS transistor; An eighth PMOS transistor having a source electrode connected to the drain electrode of the fourth PMOS transistor, a gate electrode for inputting the third borough transmission signal, and a drain electrode connected to the drain electrode of the fifth PMOS transistor; A seventh NMOS transistor having a drain electrode connected to the drain electrode of the fifth PMOS transistor, a gate electrode for inputting the third borough generation signal, and a source electrode connected to the source electrode of the fourth NMOS transistor; An eighth NMOS transistor having a drain electrode connected to the drain electrode of the fifth PMOS transistor, a gate electrode for inputting the second borough generation signal, and a source electrode connected to the source electrode of the fifth NMOS transistor; A ninth NMOS transistor having a drain electrode connected to the drain electrode of the fifth PMOS transistor, a gate electrode for inputting the first borough generation signal, and a source electrode connected to the source electrode of the sixth NMOS transistor; And a third inverter for inverting a signal from a common point between the fifth PMOS transistor and the fifth NMOS transistor. 2. The apparatus of claim 1, wherein the second cell comprises: a fourth inverter for inverting the borough transmission signal; A tenth NMOS transistor configured to transmit the bore transmission signal in response to the bore generation signal; A ninth PMOS transistor configured to transmit an output signal of a fourth inverter in response to the inverted signal of the bore generation signal; And a third CMOS transmission gate configured to transmit the borrow generation signal in response to the borrow transmission signal. 2. The subtractor according to claim 1, wherein the subtractor repeats the same structure every 16 bits and increases one subtraction level.