KR940010349A - Structure of SRAM cell - Google Patents

Structure of SRAM cell Download PDF

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Publication number
KR940010349A
KR940010349A KR1019920018962A KR920018962A KR940010349A KR 940010349 A KR940010349 A KR 940010349A KR 1019920018962 A KR1019920018962 A KR 1019920018962A KR 920018962 A KR920018962 A KR 920018962A KR 940010349 A KR940010349 A KR 940010349A
Authority
KR
South Korea
Prior art keywords
vss
bit line
sram cell
line
ram cell
Prior art date
Application number
KR1019920018962A
Other languages
Korean (ko)
Other versions
KR960010069B1 (en
Inventor
권경국
장태식
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920018962A priority Critical patent/KR960010069B1/en
Publication of KR940010349A publication Critical patent/KR940010349A/en
Application granted granted Critical
Publication of KR960010069B1 publication Critical patent/KR960010069B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits

Abstract

본 발명은 로우 Vss 특성을 개선시키기에 적당하도록 한 에스 램 셀의 구조에 관한 것으로 한 셀의 비트라인()과 비트라인(B/L) 사이에 Vss선의 Vss콘택을 형성하여 비트라인(B/L)과 비트라인()간의 전위차(Vss)를 없애므로 로우 Vas의 특성의 저하를 방지할 수 있게 한 것이다.The present invention relates to the structure of an S-RAM cell that is suitable for improving the low Vss characteristics. ) Form a Vss contact of the Vss line between the bit line (B / L) and the bit line (B / L) and the bit line ( By eliminating the potential difference (Vss) between), it is possible to prevent the deterioration of the characteristics of the row Vas.

Description

에스 램 셀의 구조Structure of SRAM cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본발명 에스 램 셀의 회로도,3 is a circuit diagram of the present invention, the S-RAM cell,

제4도는 제3도에서의 Vss콘택을 설명하기 위한 단면도,4 is a cross-sectional view for explaining the Vss contact in FIG.

제5도는 본발명에 에스 램 셀의 레이 아웃도.5 is the layout of the S-RAM cell in the present invention.

Claims (1)

에스 램 셀에 있어서, 한 셀(d)의 비트라인(B/L)과 비트라인() 사이에 Vss선의 Vss콘택이 형성되어 구성된 에스 램 셀의 구조.In an S-RAM cell, a bit line B / L and a bit line of one cell d ) The structure of the S-RAM cell formed by forming a Vss contact of the Vss line. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920018962A 1992-10-15 1992-10-15 Structure of sram cell KR960010069B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920018962A KR960010069B1 (en) 1992-10-15 1992-10-15 Structure of sram cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920018962A KR960010069B1 (en) 1992-10-15 1992-10-15 Structure of sram cell

Publications (2)

Publication Number Publication Date
KR940010349A true KR940010349A (en) 1994-05-26
KR960010069B1 KR960010069B1 (en) 1996-07-25

Family

ID=19341203

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920018962A KR960010069B1 (en) 1992-10-15 1992-10-15 Structure of sram cell

Country Status (1)

Country Link
KR (1) KR960010069B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100406760B1 (en) * 2001-11-16 2003-11-21 신코엠 주식회사 Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100406760B1 (en) * 2001-11-16 2003-11-21 신코엠 주식회사 Semiconductor memory device

Also Published As

Publication number Publication date
KR960010069B1 (en) 1996-07-25

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