KR940010045A

KR940010045A - Synchronous pattern recording and detection circuit of digital recording and reproducing apparatus

Info

Publication number: KR940010045A
Application number: KR1019920018967A
Authority: KR
Inventors: 김병수
Original assignee: 윤종용; 삼성전자 주식회사
Priority date: 1992-10-15
Filing date: 1992-10-15
Publication date: 1994-05-24
Also published as: KR0154696B1

Abstract

디지탈 기록/재생장치에 관한 것으로, 특히 디지탈 기록/재생장치의 기록 정보에 동기패턴을 삽입하여 기록하고 상기 삽입된 동기패턴을 검출하여 에러없이 기록정보를 재생도록하는 디지탈 기록/재생장치에 관한 것이다.The present invention relates to a digital recording / reproducing apparatus, and more particularly, to a digital recording / reproducing apparatus for inserting and recording a synchronization pattern into recording information of a digital recording / reproducing apparatus, and detecting the inserted synchronization pattern to reproduce recording information without error. .

상기의 장치는 재생시 기록 정보어와의 동기화를 위해 일정구간의 정보어 사이에 상기 정보어와 구별되는 동기 패턴을 삽입하여 기록하고, 재생시 상기 동기 패턴을 검출하여 정보어 단위로 재생 데이터를 전송하는 데이터 전송기를 상기 검출된 동기패턴에 동기하여 전송한다.The apparatus inserts and records a synchronization pattern distinguished from the information word between information words at a predetermined interval for synchronization with recording information words during reproduction, and detects the synchronization pattern during transmission and transmits the reproduction data in units of information words. The data transmitter is transmitted in synchronization with the detected sync pattern.

상기와 같이 정보어를 기록하고, 재생함으로써 헤드의 초기위치에 따라 발생되는 데이터 재생의 에러를 방지할 수 있다.By recording and reproducing the information word as described above, it is possible to prevent an error of data reproduction occurring in accordance with the initial position of the head.

Description

Synchronous pattern recording and detection circuit of digital recording and reproducing apparatus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 디지탈 기록 재생 장치의 동기패턴 기록회로도,2 is a synchronization pattern recording circuit diagram of the digital recording and reproducing apparatus according to the present invention;

제3도는 본 발명에 따른 디지탈 기록 재생 장치의 동기패턴 검출회로도,3 is a synchronization pattern detection circuit diagram of the digital recording and reproducing apparatus according to the present invention;

제4도는 제2도의 동작 타이밍도이다.4 is an operation timing diagram of FIG.

Claims

A synchronous pattern recording and detecting circuit of a digital recording / reproducing apparatus for recording digital information words on a magnetic recording medium through a head, picking up information recorded on the recording medium, and outputting a waveform, and outputting the recording information words, A synchronization pattern insertion means for switching in response to the synchronization pattern insertion control signal input at a period, and outputting a synchronization pattern; a first divider for dividing a main clock of a predetermined period by the number of bits of the information word and outputting a data latch clock; A latch circuit for latching parallel data output from the synchronization pattern inserting means and outputting latch data in response to an input of a data latch clock output from the first divider; and parallel data latched and output from the latch circuit. Shifted by the main clock, converted into serial data, and supplied to the head Data generation means, reproduction data detection means for converting the picked-up serial data input by the main clock into parallel data, and parallel data output from the reproduction data detection means in response to an input of a data transmission clock. A reproduction data transmission means for latching and transmitting the reproduction data as the reproduction data, and a synchronization reproduction signal generation means for comparing the parallel data output from the reproduction data detection means with a preset synchronization pattern and outputting a data synchronization reproduction signal when the two values match. And a data transmission clock generating means for dividing the main clock by the number of bits of the information word in synchronization with the synchronous reproduction signal output from the synchronous reproduction signal generating means, and outputting the main clock to the data transmission clock of the reproduction data transmission means. Circuit, characterized in that the configuration.

The synchronization pattern inserting unit of claim 1, wherein the sync pattern inserting unit selects and outputs an upper nibble bit of a recording information word or an upper nibble bit of a sync pattern according to logic of the sync pattern insert control signal, and the sync pattern. And a second multiplexer (32b) for selecting and outputting the lower nibble bit of the write information word or the lower nibble bit of the synchronization pattern according to the logic of the insertion control signal.

A synchronization pattern recording circuit of a digital information recording apparatus for recording a digital information word to a magnetic recording medium through a head, wherein the recording information word (W-DW) and the synchronization pattern (SPT) are inputted to the recording information word (W-DW). And a synchronization pattern inserter 32 for selecting and outputting the synchronization pattern SPT in response to the synchronization pattern insertion control signal Sync-s, and a predetermined clock CLK to output the number of bits of the information word. The sync pattern inserter (1) is divided in response to an input of a first divider (34) for outputting the data latch clock (DLC) and a data latch clock (DLC) output from the first divider (34). The latch circuit 36 latches the parallel data outputted from the 32 and outputs the latch data L-DATA, and the parallel data L-DATA latched and outputted from the latch circuit 36 is clocked. Shift by (CLK) to convert to serial data (SD) and output to a write amplifier Circuit comprising a PSC (38).

The synchronization pattern inserter 32 selects and outputs the upper nibble bits of the recording information word or the upper nibble bits of the synchronization pattern according to the logic of the synchronization pattern insertion control signal Sync-s. And a second multiplexer (32b) for selecting and outputting a lower nibble bit of a write information word or a lower nibble bit of a sync pattern input according to the logic of the sync pattern insertion control signal.

In a synchronization pattern detecting circuit of a digital recording / reproducing apparatus for recording a digital information word and a synchronization pattern to be recorded on a magnetic recording medium through a head, and reproducing the recorded digital information word, which is inputted by a predetermined clock CLK. The SPC 40 converts serial data P-SD into parallel data PD and outputs the parallel data PD, and the parallel data PD output from the SPC 40 in response to an input of the data transfer clock DTC. The latch circuit 42 for latching and transmitting the reproduced data and the parallel data PD output from the SPC 40 and the preset synchronization pattern SPT are compared with each other and the data synchronization and reproduction signals are matched when the two values match. A comparator 44 for outputting RET, and the predetermined clock CLK is divided by the number of bits of the recording information word in synchronization with the synchronization signal and the reproduction signal RET output from the comparator 44, This is the data transmission clock of the latch circuit 42 Circuit, characterized in that consists of (DTC) The dispenser (46) for outputting a.

※ Note: The disclosure is based on the initial application.