KR940009854A - Transmission Unit Control Method of Direct Memory Access (DMA) Controller - Google Patents
Transmission Unit Control Method of Direct Memory Access (DMA) Controller Download PDFInfo
- Publication number
- KR940009854A KR940009854A KR1019920019195A KR920019195A KR940009854A KR 940009854 A KR940009854 A KR 940009854A KR 1019920019195 A KR1019920019195 A KR 1019920019195A KR 920019195 A KR920019195 A KR 920019195A KR 940009854 A KR940009854 A KR 940009854A
- Authority
- KR
- South Korea
- Prior art keywords
- transmission unit
- dma
- controller
- control method
- memory access
- Prior art date
Links
Landscapes
- Computer And Data Communications (AREA)
Abstract
본 발명은 블럭형 입,출력 제어기의 효율 향상을 도모코자 하여 전송량에 따라 기본 전송단위를 결정하여 주기 위한 제어방법에 관한 것이다. 이와같은 본 발명은 DMA제어기로부터 공급하는 기본 전송단위들 중에서 전송량이 기본 전송 단위로 나누어 떨어질 수 있는 전송 단위로 제어함으로써, 별도의 기억 공간을 확보하지 않아도 될 뿐만 아니라 재차 프로그래밍을 필요로 하지 않으며 프로그래밍의 단순화를 도모코자 할 수가 있어 DMA동작을 보다 효율적으로 제어할 수가 있는 것이다.The present invention relates to a control method for determining a basic transmission unit according to the transmission amount to improve the efficiency of the block-type input and output controller. As described above, the present invention controls the transmission unit in which the transfer amount can be divided into the basic transmission units among the basic transmission units supplied from the DMA controller, so that not only a separate memory space is required but also no programming is required again. The DMA operation can be controlled more efficiently by simplifying the operation.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 제어방법에 관련된 DMA 제어장치의 블럭 구성도,2 is a block diagram of a DMA control apparatus related to a control method according to the present invention;
제3도는 본 발명에 따른 DMA 제어기의 기본 전송 단위 제어방법을 설명하기 위한 플로우 챠트도를 나타낸 것으로서,3 is a flowchart illustrating a method of controlling a basic transmission unit of a DMA controller according to the present invention.
(가)는 기본 전송단위가 2가지(예 : 2바이트, 1바이트)인 경우,(A) means that if there are two basic transmission units (eg 2 bytes, 1 byte),
(나)는 기본전송 단위가 3가지(예: 4비트, 2바이트, 1바이트)경우를 각각 나타낸 것이다.(B) shows three cases of basic transmission unit (eg 4 bit, 2 byte, 1 byte).
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019195A KR940009854A (en) | 1992-10-19 | 1992-10-19 | Transmission Unit Control Method of Direct Memory Access (DMA) Controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019195A KR940009854A (en) | 1992-10-19 | 1992-10-19 | Transmission Unit Control Method of Direct Memory Access (DMA) Controller |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940009854A true KR940009854A (en) | 1994-05-24 |
Family
ID=67210080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920019195A KR940009854A (en) | 1992-10-19 | 1992-10-19 | Transmission Unit Control Method of Direct Memory Access (DMA) Controller |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940009854A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020004701A (en) * | 2000-07-07 | 2002-01-16 | 배길훈 | Fluid damper type speed sensitive power steering gear |
KR100813267B1 (en) * | 2006-09-19 | 2008-03-13 | 삼성전자주식회사 | Method and apparatus to set transfer unit of data process system |
-
1992
- 1992-10-19 KR KR1019920019195A patent/KR940009854A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020004701A (en) * | 2000-07-07 | 2002-01-16 | 배길훈 | Fluid damper type speed sensitive power steering gear |
KR100813267B1 (en) * | 2006-09-19 | 2008-03-13 | 삼성전자주식회사 | Method and apparatus to set transfer unit of data process system |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
HK1015479A1 (en) | High speed data input-output device which fetches data into internal memory and performs operations on the data before outputting the data | |
KR880003252A (en) | Microprocessor | |
KR940009854A (en) | Transmission Unit Control Method of Direct Memory Access (DMA) Controller | |
JPS57182257A (en) | Data interchange system of data processing system | |
KR880009306A (en) | Direct memory access control unit | |
JPS5358731A (en) | Memory address extension method | |
JPS56116138A (en) | Input and output controller | |
JPS57130278A (en) | Storage device | |
JPS6433656A (en) | Control system for transfer of data | |
JPS56111905A (en) | Programmable sequence controller | |
ATE175287T1 (en) | SIGNAL PROCESSOR | |
JPS54145447A (en) | Input-output control system | |
JPS57212517A (en) | Operation status changing system of computer | |
JPS6441952A (en) | Data transferring control system | |
KR880014450A (en) | Real-time data input / output device | |
JPS54104745A (en) | Control system for data transfer | |
JPS5785147A (en) | Microprogram control device | |
JPS54142025A (en) | Address system | |
JPS54114134A (en) | Variable length data transfer system | |
JPS54161855A (en) | Input/output control system | |
TW259868B (en) | Delay circuit | |
ES8104594A1 (en) | Input*output control unit | |
JPS5671109A (en) | Input control method of sequence controller | |
RU98100973A (en) | COMPUTER SYSTEM BASED ON THE MATRIX OF PROCESSOR ELEMENTS | |
JPS5797109A (en) | Sequence controller |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |