KR940008082A - Semiconductor Memory and Manufacturing Method - Google Patents

Semiconductor Memory and Manufacturing Method Download PDF

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Publication number
KR940008082A
KR940008082A KR1019920016153A KR920016153A KR940008082A KR 940008082 A KR940008082 A KR 940008082A KR 1019920016153 A KR1019920016153 A KR 1019920016153A KR 920016153 A KR920016153 A KR 920016153A KR 940008082 A KR940008082 A KR 940008082A
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KR
South Korea
Prior art keywords
dielectric film
high dielectric
semiconductor memory
memory device
electrode
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KR1019920016153A
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Korean (ko)
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권기원
강창석
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김광호
삼성전자 주식회사
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Priority to KR1019920016153A priority Critical patent/KR940008082A/en
Publication of KR940008082A publication Critical patent/KR940008082A/en

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 고우전막의 캐퍼시터장치 및 그제조방법에 관한 것으로,도전물질인 제1극과 제2극 사이에 고유전막이 형성되어 이루어진 캐퍼시터를 포함하는 반도체 기억장치의 제조방법에 있어서, 상기 제1전극상에 다공질의 고유전막을 저온 증착시키는 공정과, 상기 고유전막을 고온에서 열처리시키는 공정을 포함하여 이루어지는것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor device of a high dielectric film and a method of manufacturing the same. And depositing a porous high dielectric film on the electrode at low temperature, and heat treating the high dielectric film at high temperature.

상기 제1전극상에 다공질의 고유전막을 저온 증착시키는 공정과, 상기 고유전막을 고온에서 열처리시키는 공정을 포함하여 이루어지는 것을 특징으로 한다.And depositing a porous high dielectric film on the first electrode at low temperature, and heat treating the high dielectric film at high temperature.

본 발명에 의하면 고유전막의 막질이 치밀하게 변화하여 캐퍼시터의 누설전류밀도가 현저히 감소하는 등 고신뢰성의 캐퍼시터를 얻을 수 있다.According to the present invention, a highly reliable capacitor can be obtained such that the film quality of the high dielectric film is changed densely and the leakage current density of the capacitor is significantly reduced.

Description

반도체 기억장치 및 그 제조방법Semiconductor Memory and Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의해 제조된 캐퍼시터의 단면도.1 is a cross-sectional view of a capacitor produced by the present invention.

제2도는 본 발명에 사용한 산화탄탈륨 증착 설비도.2 is a tantalum oxide deposition equipment used in the present invention.

제3도는 본 발명에 따른 유전막의 증착온도와 증착속도의 관계 그래프.3 is a graph of the relationship between the deposition temperature and the deposition rate of the dielectric film according to the present invention.

제4도는 본 발명에 따른 유전막의 두께 변화를 나타낸 그래프.4 is a graph showing a change in the thickness of the dielectric film according to the present invention.

Claims (12)

도전 물질로 된 제1전극과 제2전극 사이에 고유전막이 형성되어 이루어진 캐퍼시터를 포함하는 반도체 기억 장치의 제조방법에 있어서, 상기 제1전극 상에 다공질의 고유전막을 저온증착시키는 공정과, 상기 고유 전막을 고온에서 열처리시키는 공정을 포함하여 이루어지는 반도체 기억장치의 제조방법.A method of manufacturing a semiconductor memory device comprising a capacitor formed by forming a high dielectric film between a first electrode and a second electrode made of a conductive material, the method comprising: depositing a porous high dielectric film on the first electrode at low temperature; A method of manufacturing a semiconductor memory device comprising the step of heat-treating a high dielectric film at a high temperature. 제1항에 있어서, 상기 고유전막은 천이금속산화물임을 특징으로 하는 반도체 기억장치의 제조방법.2. The method of claim 1, wherein the high dielectric film is a transition metal oxide. 제2항에 있어서, 상기천이금속산화물은 산화탄탈륨(Ta2O5)임을 특징으로 하는 반도체 기억장치의 제조방법.The method of claim 2, wherein the transition metal oxide is tantalum oxide (Ta 2 O 5 ). 제3항에 있어서, 상기 Ta2O의 증착은 온도410℃이하에서 수행하는 것을 특징으로 하는 반도체 기억장치의 제조방법.The method of claim 3, wherein the deposition of Ta 2 O is performed at a temperature of 410 ° C. or less. 제 1항에 있어서, 상기 고유전막의 증착은 저압화학 기상증착법에 의해 수행하는 것을 특징으로 하는 반도체 기억장치의 제조방법.The method of claim 1, wherein the deposition of the high dielectric film is performed by a low pressure chemical vapor deposition method. 제1항에 있어서,상기 고유전막에 대한 열처리는 온도 650℃∼950℃범위이내에서 수행하는 것을 특징으로 하는 반도체 기억장치의 제조방법.The method of claim 1, wherein the heat treatment of the high dielectric film is performed at a temperature of 650 ° C. to 950 ° C. 6. 제6항에 있어서, 상기 고유전막에 대한 열처리온도는 800℃에서 수행하는 것을 특징으로 하는 반도체 기억장치의 제조방법.The method of manufacturing a semiconductor memory device according to claim 6, wherein the heat treatment temperature for the high dielectric film is performed at 800 占 폚. 제1항에 있어서, 상기 고유전막에 대한 열처리는 산소가스, 질소가스 및 산소와 질소의 혼합가스 중 어느 하나의 분위기하에 수행되는 것을 특징으로 하는 반도체 기억장치의 제조방법.The method of manufacturing a semiconductor memory device according to claim 1, wherein the heat treatment of the high dielectric film is carried out in an atmosphere of any one of oxygen gas, nitrogen gas and mixed gas of oxygen and nitrogen. 도전물질로 된 제1전극과 제2전극사이에 고유전막이 형성되어 이루어진 캐퍼시터를 포함하는 반도체 기억장치에 있어서, 상기 제1전극상에 제1전극의 산화물층이 형성되어 있고, 상기 산화물층상에 저온증착 후 고온에서 열처리한 고유전막이 형성되어 있는 것을 특징으로 하는 반도체 기억장치.A semiconductor memory device comprising a capacitor having a high dielectric film formed between a first electrode and a second electrode made of a conductive material, wherein an oxide layer of the first electrode is formed on the first electrode, and on the oxide layer. A semiconductor memory device characterized in that a high-k dielectric film heat-treated at high temperature after low temperature deposition is formed. 제9항에 있어서, 상기 고유전막은 천이금속 산화물임을 특징으로 하는 반도체 기억장치.10. The semiconductor memory device according to claim 9, wherein the high dielectric film is a transition metal oxide. 제10항에 있어서, 상기 천이금속 산화물은 산화탄탈륨(Ta2O5)임을 특징으로 하는 반도체 기억장치.The semiconductor memory device according to claim 10, wherein the transition metal oxide is tantalum oxide (Ta 2 O 5 ). 제11항에 있어서, 상기 산화탄탈륨은 헥사고날 구조의 8상을 포함하고 있는 것을 특징으로 하는 반도체 기억장치.12. The semiconductor memory device according to claim 11, wherein said tantalum oxide contains eight phases of hexagonal structure. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019920016153A 1992-09-04 1992-09-04 Semiconductor Memory and Manufacturing Method KR940008082A (en)

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