KR940008082A - Semiconductor Memory and Manufacturing Method - Google Patents
Semiconductor Memory and Manufacturing Method Download PDFInfo
- Publication number
- KR940008082A KR940008082A KR1019920016153A KR920016153A KR940008082A KR 940008082 A KR940008082 A KR 940008082A KR 1019920016153 A KR1019920016153 A KR 1019920016153A KR 920016153 A KR920016153 A KR 920016153A KR 940008082 A KR940008082 A KR 940008082A
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- KR
- South Korea
- Prior art keywords
- dielectric film
- high dielectric
- semiconductor memory
- memory device
- electrode
- Prior art date
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- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 고우전막의 캐퍼시터장치 및 그제조방법에 관한 것으로,도전물질인 제1극과 제2극 사이에 고유전막이 형성되어 이루어진 캐퍼시터를 포함하는 반도체 기억장치의 제조방법에 있어서, 상기 제1전극상에 다공질의 고유전막을 저온 증착시키는 공정과, 상기 고유전막을 고온에서 열처리시키는 공정을 포함하여 이루어지는것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor device of a high dielectric film and a method of manufacturing the same. And depositing a porous high dielectric film on the electrode at low temperature, and heat treating the high dielectric film at high temperature.
상기 제1전극상에 다공질의 고유전막을 저온 증착시키는 공정과, 상기 고유전막을 고온에서 열처리시키는 공정을 포함하여 이루어지는 것을 특징으로 한다.And depositing a porous high dielectric film on the first electrode at low temperature, and heat treating the high dielectric film at high temperature.
본 발명에 의하면 고유전막의 막질이 치밀하게 변화하여 캐퍼시터의 누설전류밀도가 현저히 감소하는 등 고신뢰성의 캐퍼시터를 얻을 수 있다.According to the present invention, a highly reliable capacitor can be obtained such that the film quality of the high dielectric film is changed densely and the leakage current density of the capacitor is significantly reduced.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명에 의해 제조된 캐퍼시터의 단면도.1 is a cross-sectional view of a capacitor produced by the present invention.
제2도는 본 발명에 사용한 산화탄탈륨 증착 설비도.2 is a tantalum oxide deposition equipment used in the present invention.
제3도는 본 발명에 따른 유전막의 증착온도와 증착속도의 관계 그래프.3 is a graph of the relationship between the deposition temperature and the deposition rate of the dielectric film according to the present invention.
제4도는 본 발명에 따른 유전막의 두께 변화를 나타낸 그래프.4 is a graph showing a change in the thickness of the dielectric film according to the present invention.
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920016153A KR940008082A (en) | 1992-09-04 | 1992-09-04 | Semiconductor Memory and Manufacturing Method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920016153A KR940008082A (en) | 1992-09-04 | 1992-09-04 | Semiconductor Memory and Manufacturing Method |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940008082A true KR940008082A (en) | 1994-04-28 |
Family
ID=67147919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920016153A KR940008082A (en) | 1992-09-04 | 1992-09-04 | Semiconductor Memory and Manufacturing Method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940008082A (en) |
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1992
- 1992-09-04 KR KR1019920016153A patent/KR940008082A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
WITB | Written withdrawal of application |