KR940007292B1 - Isolating method using trench - Google Patents

Isolating method using trench Download PDF

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Publication number
KR940007292B1
KR940007292B1 KR1019910000639A KR910000639A KR940007292B1 KR 940007292 B1 KR940007292 B1 KR 940007292B1 KR 1019910000639 A KR1019910000639 A KR 1019910000639A KR 910000639 A KR910000639 A KR 910000639A KR 940007292 B1 KR940007292 B1 KR 940007292B1
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South Korea
Prior art keywords
trench
polycrystalline silicon
substrate
film
device isolation
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KR1019910000639A
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Korean (ko)
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김현종
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금성일렉트론 주식회사
문정환
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Priority to KR1019910000639A priority Critical patent/KR940007292B1/en
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Abstract

The isolation method using a trench includes the steps of forming a first polysilicon layer 3 on the overall substrate of a substrate in which a trench is formed, etching first polysilicon layer to form a sidewall polysilicon layer, forming a second polysilicon layer 14 on the overall surface of the substrate, thermal oxidizing the polysilicon layer and sidewall polysilicon layer to bury the trench with the polysilicon oxide, removing a portion of the polysilicon layer which is not formed in the trench, thereby preventing leakage current.

Description

트렌치를 이용한 소자분리 방법Device isolation method using trench

제1도는 종래의 트렌치를 이용한 소자분리 형성도.1 is a device isolation formation diagram using a conventional trench.

제2도는 본 발명의 트렌치를 이용한 소자분리 공정도.2 is a device isolation process chart using the trench of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 포토레지스트막1 substrate 2 photoresist film

3, 4 : 다결정 실리콘막 5 : 다결정 실리콘 산화막3, 4: polycrystalline silicon film 5: polycrystalline silicon oxide film

본 발명은 트렌치(Trench)를 이용한 소자분리 방법에 관한 것으로, 특히 트렌치 내부를 용이하게 메워 평탄화를 개선시킨 것이다.The present invention relates to a device isolation method using a trench, in particular to easily fill the inside of the trench to improve the planarization.

제1도는 종래의 트렌치를 이용한 소자분리영역 형성공정도이다.1 is a process diagram for forming a device isolation region using a conventional trench.

종래에는 반도체 소자를 분리시키기 위하여 제1도 (a)와 같이 기판(11) 위에 포토레지스트막(12)를 도포한 후 선택적 식각하여 분리영역에 해당하는 기판(11)을 노출시키고, 제1도 (b)와 같이 포토레지스트막(12)을 마스크로 하여 기판(11)을 식각하여 트렌치를 식각 형성한다.Conventionally, in order to separate a semiconductor device, the photoresist film 12 is coated on the substrate 11 as shown in FIG. 1A, and then selectively etched to expose the substrate 11 corresponding to the isolation region. As shown in (b), the substrate 11 is etched using the photoresist film 12 as a mask to form trenches.

제1도 (c)와 같이 제1산화막(13)을 기판전면에 형성한다.As illustrated in FIG. 1C, the first oxide film 13 is formed on the entire surface of the substrate.

그리고 제1도 (d)와 같이 상기 제1산화막(13)을 식각하여 트렌치 내부에만 남겨둔다.As shown in FIG. 1 (d), the first oxide layer 13 is etched and left only in the trench.

제1도 (e)와 같이 기판전면에 제2산화막(14)을 형성한 후 식각하여 트렌치 내부에만 남겨둔다.As shown in FIG. 1 (e), the second oxide layer 14 is formed on the entire surface of the substrate and is etched to leave only the trench.

따라서 트렌치 내부가 소자분리영역(5)으로서 제1 및 제2산화막(3)(4)에 의해 메워져 소자를 분리시킴과 아울러 기판표면의 평탄화를 이룰 수 있다.Therefore, the inside of the trench is filled with the first and second oxide films 3 and 4 as the device isolation region 5 to separate the devices and to planarize the surface of the substrate.

그러나, 상기와 같은 종래의 소자분리영역 형성방법은 여러번의 산화막(13)(14)을 형성함으로 인한 파티클(Particle)의 영향 및 여러번의 건식식각으로 인한 소자분리영역에 누설전류를 유발시키기 쉬운 결점이 있다.However, the conventional method of forming a device isolation region as described above has a drawback that it is easy to cause a leakage current in the device isolation region due to the effect of particles and the number of dry etching due to the formation of several oxide films 13 and 14. There is this.

본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로, 트렌치 식각후 트렌치의 단차를 이용하여 다결정 실리콘을 형성하고 이를 산화시킴으로써 양측벽 다결정 실리콘의 산화막 성장을 이용하여 트렌치 내부를 함몰시키는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and its purpose is to immerse the inside of the trenches using the oxide film growth of both sidewall polycrystalline silicon by forming and oxidizing polycrystalline silicon using the steps of the trench after etching. .

이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도에 의하여 상술하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings of FIG. 2.

제2도 (a)-(f)는 본 발명의 실시예에 따른 소자분리영역 형성공정도이다.2 (a)-(f) are process diagrams for forming an isolation region according to an embodiment of the present invention.

먼저 제2도 (a)와 같이 기판(1)에 포토레지스트막(2)를 도포하고 선택적 식각하여 분리영역에 해당하는 기판(1)을 노출시키고, 제2도 (b)와 같이 포토레지스트막(2)을 마스크로 하여 기판(1)을 식각하여 트렌치를 형성한다.First, as shown in FIG. 2A, a photoresist film 2 is applied to the substrate 1 and selectively etched to expose the substrate 1 corresponding to the separation region. As shown in FIG. 2B, the photoresist film is exposed. The substrate 1 is etched using (2) as a mask to form a trench.

그리고 제2도 (c)와 같이 다결정 실리콘막(3)을 형성하고 제2도 (D)와 같이 다결정 실리콘막(3)을 이방성 식각하여 단차를 이용한 측벽다결정 실리콘막을 형성한다.As shown in FIG. 2C, the polycrystalline silicon film 3 is formed, and as shown in FIG. 2D, the polycrystalline silicon film 3 is anisotropically etched to form sidewall polycrystalline silicon films using steps.

다음에, 제2도 (e)와 같이 2차로 기판전면에 걸쳐 다결정 실리콘막(4)을 형성한다. 이어서, 다결정 실리콘막(4)을 열산화시켜 다결정 실리콘 열산화막을 형성한다.Next, as shown in FIG. 2E, a polycrystalline silicon film 4 is formed over the entire surface of the substrate. Next, the polycrystalline silicon film 4 is thermally oxidized to form a polycrystalline silicon thermal oxide film.

다결정 실리콘막(4)의 열산화시 측벽 다결정 실리콘막(3)도 열산화됨으로부터 산화막이 성장되므로 트렌치내에 다결정 실리콘 열산화막(5)이 소자분리영역으로서 함몰된다.Since the sidewall polycrystalline silicon film 3 is also thermally oxidized during thermal oxidation of the polycrystalline silicon film 4, the oxide film is grown so that the polycrystalline silicon thermal oxide film 5 is recessed in the trench as an element isolation region.

최종적으로 트렌치내에만 다결정 실리콘 열산화막(5)을 남겨두고 나머지를 식각하여 제거하면 제2도(f)에 도시된 바와 같은 열산화막(5)으로 된 소자분리영역을 얻게 된다.Finally, if the polycrystalline silicon thermal oxide film 5 is left in the trench and the remaining portions are etched and removed, the device isolation region of the thermal oxide film 5 is obtained as shown in FIG.

이상과 같은 본 발명에 의하면 소자분리와 동시에 평탄화를 이룰 수 있음은 물론 한번의 산화막 형성공정으로 파티클 영향을 감소시킬 수 있으며, 건식식각 횟수를 감소시켜 소자분리영역에 유발되기 쉬운 누설전류를 방지할 수 있는 장점이 있다.According to the present invention as described above can be flattened at the same time as the isolation of the device as well as to reduce the particle effect in a single oxide film forming process, to reduce the number of dry etching to prevent the leakage current prone to the device isolation region There are advantages to it.

Claims (1)

포토레지스트막(2)을 마스크로 하여 분리영역에 해당하는 부분의 기판(1)을 식각하여 트렌치를 형성하고, 트렌치내에 산화막을 함몰시켜 소자분리영역을 형성하는 소자분리 방법에 있어서, 기판전면에 1차로 다결정 실리콘막(3)을 도포하는 공정과, 다결정 실리콘막(3)을 식각하여 측벽 다결정 실리콘막을 형성하는 공정과, 기판전면에 2차로 다결정 실리콘막(14)을 도포하는 공정과, 상기 다결정 실리콘막과 측벽 다결정 실리콘산화막을 열산화하여 트렌치를 소자분리용 다결정 실리콘 산화막(5)로 함몰시키는 공정과, 트렌치를 제외한 다결정 실리콘산화막(5)을 제거하는 공정으로 이루어지는 것을 특징으로 하는 트렌치를 이용한 소자분리방법.A device isolation method in which a trench is formed by etching a substrate 1 corresponding to a separation region using a photoresist film 2 as a mask, and a device isolation region is formed by recessing an oxide film in the trench to form a device isolation region. Firstly applying the polycrystalline silicon film 3, etching the polycrystalline silicon film 3 to form a sidewall polycrystalline silicon film, secondly applying the polycrystalline silicon film 14 to the front of the substrate, and A trench comprising a step of thermally oxidizing the polycrystalline silicon film and the sidewall polycrystalline silicon oxide film to dent the trench into the polycrystalline silicon oxide film 5 for device isolation, and removing the polycrystalline silicon oxide film 5 except the trench. Device separation method using.
KR1019910000639A 1991-01-16 1991-01-16 Isolating method using trench KR940007292B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010009388A (en) * 1999-07-09 2001-02-05 김영환 Manufacturing method for trench isolation in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010009388A (en) * 1999-07-09 2001-02-05 김영환 Manufacturing method for trench isolation in semiconductor device

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