KR940006717Y1 - Reading and writing circuit in vtr - Google Patents

Abstract

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Description

VTR video signal writing and reading circuit

1A and 1B are conventional circuit diagrams shown in block diagrams.

2 is a circuit diagram of the present invention shown in a block diagram.

3 is a waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

10: VCO 18: n multiplied PLL

12 switch 20 gate array

14: Servo IC 22: Reference Voltage Generator

16: pulse generator

The present invention is a VTR having a field memory to store in a memory while exporting a real-time image, and in particular, the master clock used for writing or reading the sub reference clock and image information for exporting a real-time image is locked by phase locking. The present invention relates to a VTR video signal write readout circuit with individualized image stabilization.

In a VTR having a field memory controller and a field memory, in which a picture in the VTR is noise suppressed or a pulse image is processed for special effects, a conventional method for locking a real time picture and a memory read picture is defined in the first 1a. As shown in FIG. 1B, there are two methods.

First, the method of reading using external synchronization is the same as that of FIG. 1a. The video signals are respectively input to the analog processing block stage 1 including the A / D converter and the sync separator 2 separating the sync from the input signal. In the synchronous separator, the horizontal synchronous signal and the vertical synchronous signal are output and applied to the AFC circuit, and the output from the analog processing block stage is input to the memory controller 3 together with the output of the AFC (that is, the synchronization signals HS and VS). . The memory controller is in contact with the field memory 4 and the controller output is output to a D / A converter (DAC) so as to output a video signal from the converter.

Depending on the intensive description, the method is a method of synchronously separating a video input signal which may be somewhat unstable and using it as a memory controller read reference signal.

Alternatively, a read method using a synchronous generator as in the case of 1b, the video input signal is applied to the analog processing block stage 1 including the A / D converter and its output is input to the memory controller 3. The synchronization generator 6 which supplies the horizontal synchronization signal HS and the vertical synchronization signal VS to the memory controller receives a color subcarner 5sc detected from the video input and also has a PLL having a crystal oscillator 7. It receives the frequency (fsc ') output from the oscillator. The memory controller is in contact with the field memory and this controller output is applied to the D / A converter to obtain a video output signal. In other words, this method uses a synchronization generator IC to create horizontal and vertical synchronization and use it as a read reference signal.

In the conventional method described above, the first described method is free run due to unstable horizontal synchronization and reference signal of AFC in places where RF is not good at various shifts, so that the signal is synchronized with the signal from the actual tape. (skew) occurs or the screen shakes.

In addition, the second described scheme is designed with accurate calculations closest to the standard signal, and uses a synchronization generator IC that divides the master clock to generate synchronization, or the synchronization generator is embedded inside the memory controller.

However, even in this case, the VTR regeneration signal is a non-standard signal, and the oscillation block and locking of the crystal oscillator (or Y / C color subcarrier) used in the servo and the field memory controller cannot be guaranteed. Since the number of clocks used by dividing at is not exactly the standard signal, these errors are accumulated, and the synchronization of the switching between the memory read image and the image detected from the video head is deviated, and this error is caused by the vertical shaking of the screen.

An object of the present invention is to solve the above problems, and to provide a circuit for preventing the image shaking up and down by phase locking a reference clock of a servo for exporting a real-time image and a master clock used for writing or reading image information.

The circuit of the present invention constructed according to the purpose of the present invention is shown in block diagram in FIG. 3 is a timing diagram relating to the circuit of FIG.

The configuration and operation of the present invention will be described according to the drawings.

In the circuit configuration of the present invention, as shown in FIG. 2, the VCO 10 connected to the variable resistor R1 for free-run adjustment applies the output frequency fsc 'to the switch 12. The switch output, which is switched to the digital mode, is applied to the thermo IC 14 as a servo master clock, which applies a 30 Hz servo reference signal C to the pulse generator 16. The pulse generator 16 receives a servo reference signal of 30 Hz to generate a ladder-shaped waveform based on the rising edge. The frequency fsc from Y / C is applied to the switch 12 and the n-multiplied PLL 18 which output the servo master clock, respectively.

The master clock (n fsc), which is the output of the n-multiplied PLL, is applied to the gate array 20 for field memory control, and a memory-based 30 Hz signal from the gate array 2 is applied to the monostable multivibrator (M. M). do. The M. M is connected with a variable resistor R2 connected to a power supply Vcc for delay adjustment. This M. M output is applied to the sample-hold circuit S / H together with the pulse generator 16 output as a sampling pulse and this output is applied to the VCO along with the reference voltage generator 22 signal. The gate array A divider, a 30 / fec divider, and a synchronization generator 24 are included and horizontal and vertical synchronization signals are output.

When the power is applied, the VCO 10 oscillates and the oscillation frequency fsc 'is applied to the servo IC 14, and there is a divider (not shown) in the servo IC, thereby generating a servo reference signal of 30 Hz. 3 (c)).

On the other hand, the fsc signal from the Y / C is input to the n-multiplied PLL 18 and used as a reference signal for the PLL operation of the n-fsc VCO.

The n fsc signal is divided into a value different from that of the servo IC by the processing for memory control in the memory controller gate array, thereby producing a memory reference signal (see FIG. 3A) having an error from the servo reference signal. When the field is written between the deblocks (servo and field memory controller), they do not coincide with each other in real time, and there is a misalignment between the synchronization signals of the images written in the servo and the images read out from the memory controller. According to the circuit of the present invention, the error produced by the divider of the two blocks is applied to the fsc VCO as an error voltage using a phase comparator (pulse generator and S / H circuit).

Therefore, the memory controller operates on the basis of the fsc signal extracted from the video signal, and the synchronization results of the video signal read out based on this signal as the memory reference signal. The servo reference signal, which is the result of the servo operation, is fed back so as to be operated to follow the memory reference signal.

In addition, as shown in FIG. 3 (c), the monostable multivibrator is a vibrator capable of determining whether to lock both signals in a predetermined phase. 3 (b) shows sampling pulses, and FIGS. 3 (d) and 3 (e) show ladder pulses and S / H voltages, respectively.

As a master clock for servo operation in the VTR, the conventional VTR uses a color subcarrier signal (fsc) from Y / C. However, the present invention switches to a newly formed fsc 'signal when the clock signal is switched to digital mode. When digital mode is canceled, it switches to fsc from Y / C.

Claims (1)

In a VTR having a field memory, the output of a switch that receives the VCO output and Y / C output and operates in digital mode is applied to the servo IC, and the Y / C output is also applied to the n-multiplied PLL so that the output is a field. It is applied to a gate array that performs memory control and outputs horizontal and vertical synchronization signals, and another output of the gate array is applied to S / H through a monostable multivibrator, and at the same time, the output of the servo IC is passed through a pulse generator. And an output from the S / H and an output from a reference voltage generator are applied to the VCO.