KR940006675B1 - Manufacturing method of mosfet - Google Patents
Manufacturing method of mosfet Download PDFInfo
- Publication number
- KR940006675B1 KR940006675B1 KR1019910015998A KR910015998A KR940006675B1 KR 940006675 B1 KR940006675 B1 KR 940006675B1 KR 1019910015998 A KR1019910015998 A KR 1019910015998A KR 910015998 A KR910015998 A KR 910015998A KR 940006675 B1 KR940006675 B1 KR 940006675B1
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- silicide
- layer
- gate
- deposited
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005137 deposition process Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000001459 lithography Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
제1도는 종래의 모스펫 공정 단면도.1 is a cross-sectional view of a conventional MOSFET process.
제2도는 본 발명의 모스펫 공정 단면도.2 is a cross-sectional view of the MOSFET process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 폴리실리콘1 substrate 2 polysilicon
3 : 측벽 4 : 제1폴리실리콘3: side wall 4: first polysilicon
5 : 티타늄 6 : 제2폴리실리콘5: titanium 6: second polysilicon
7 : 실리사이드 8 : 절연층7: silicide 8: insulation layer
9 : 메탈9: metal
본 발명은 반도체 소자에 관한 것으로, 특히 디램(DRAM)급 소자의 메모리 셀에 LDD(Lightly Dioped Drain) 구조를 형성하기에 적당하도록 한 모스펫(MOS FET)제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a MOSFET (MOS FET), which is suitable for forming an LDD (Lightly Dioped Drain) structure in a memory cell of a DRAM class device.
종래의 모스펫 제조공정은 제1도(a)에 도시된 바와 같이 기판(1)에 필드영역과 액티브 영역을 구분하여 전면에 폴리실리콘(2)을 증착하고 패터닝(Patterning) 하므로 게이트를 형성한 후 소오스/드레인을 형성하기 위한 이온을 주입한다.In the conventional MOSFET manufacturing process, as shown in FIG. 1 (a), the polysilicon 2 is deposited and patterned on the front surface by dividing the field region and the active region on the substrate 1 to form a gate. Ions are implanted to form the source / drain.
그리고 제1도(b)와 같이 측벽(3)을 형성하고 제1도(c)와 같이 전면에 티타늄을 스퍼터링한 후 어닐(Anneal)하여 실리사이드(Silicide)(빗금친 부분)(7)을 형성하며 이어 제1도(d)와 같이 잔여 티타늄을 제거한다.Next, as shown in FIG. 1 (b), the sidewall 3 is formed, and as shown in FIG. 1 (c), titanium is sputtered on the front surface and then annealed to form a silicide (hatched portion) 7. Subsequently, residual titanium is removed as shown in FIG.
다음에 제1도(e)와 같이 전면에 절연층(8)을 형성하고 콘택을 형성하여 메탈(9)을 증착한다. 그리나, 상기와 같은 종래 기술에 있어서는 소오스/드레인 영역에 실리사이드가 파고들어가 기판(1) 표면이 손상되기 때문에 LDD구조를 형성할 수 없으며, 자기 정합(Self-align)의 이득이 적은 결점이 있다.Next, as illustrated in FIG. 1E, an insulating layer 8 is formed on the entire surface, and a contact is formed to deposit the metal 9. However, in the prior art as described above, since silicide penetrates into the source / drain regions and the surface of the substrate 1 is damaged, the LDD structure cannot be formed, and there is a drawback of low self-alignment gain.
본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로 실리사이드를 기판 표면에 접촉되지 않게 기판표면과 실리사이드 사이에 폴리실리콘을 형성하여 LDD구조를 이룰 수 있는 모스펫을 제조하는 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to provide a method for manufacturing a MOSFET capable of forming an LDD structure by forming polysilicon between the surface of the substrate and the silicide so that the silicide does not contact the substrate surface. .
본 발명의 또 다른 목적은 자기 정합의 이득을 증가시킬 수 있는 방법을 제공하는데 있다.It is yet another object of the present invention to provide a method which can increase the gain of self matching.
이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to FIG. 2.
먼저 (a)와 같이 기판(1)에 필드영역과 액티브영역을 한정하여 필드영역에 필드산화막을 형성하고 액티브영역에 게이트 산화막(2a)을 형성한 다음 폴리실리콘(2) 및 캡게이트 산화막(2b)을 증착하고 캡게이트산화막(2b), 폴리실리콘(2)과 게이트 산화막을 선택적으로 제거하여 게이터를 형성한 후 게이트를 마스크로 이용하여 기판(1) 저농도 n형 이온주입으로 소오스/드레인영역을 형성한다.First, as shown in (a), the field region and the active region are defined in the substrate 1 to form a field oxide film in the field region, and the gate oxide film 2a is formed in the active region, followed by the polysilicon 2 and the capgate oxide film 2b. ), And the gate gate is formed by selectively removing the cap gate oxide film 2b, the polysilicon 2, and the gate oxide film, and then source / drain regions are formed by using a gate as a mask with low concentration n-type ion implantation. Form.
다음에 (b)와 같이 전면에 절연막을 증착하고 에치백하여 게이트 측벽에 절연막 측벽(3)을 형성하고 (c)와 같이 전면에 고농도 n형으로 도핑된 제1폴리실리콘(4)을 증착한 후 그 위에 (d)와 같이 티타늄(5)을 증착한다.Next, as shown in (b), an insulating film is deposited on the entire surface and etched back to form an insulating film sidewall 3 on the gate sidewall, and as shown in (c), the first polysilicon 4 doped with a high concentration n-type is deposited on the front surface. Then, titanium (5) is deposited thereon as shown in (d).
그리고 (e)와 같이 상기 티타늄(5) 위에 다시 제2폴리실리콘(6)을 증착하고 (F)와 같이 열처리(Anealing)하여 하나의 실리사이드(7)을 형성한다.Then, as shown in (e), the second polysilicon 6 is again deposited on the titanium 5, and annealing is performed to form one silicide 7 as shown in (F).
이때, 제1폴리실리콘(4)을 두껍게 증착하고, 제2폴리실리콘(6)은 얇게 증착하여 열처리 공정시 제1폴리실리콘(4) 상부와 티타늄(5) 및 제2폴리실리콘(6)만 Ti-실리사이드가 되도록 하여 남아 있는 고농도 n형 제1폴리실리콘(4)을 소오스 및 드레인 영역으로 작용하여 LDD구조를 갖도록 한다.At this time, the first polysilicon 4 is deposited thickly, and the second polysilicon 6 is deposited thinly so that only the upper part of the first polysilicon 4 and the titanium 5 and the second polysilicon 6 during the heat treatment process. It becomes Ti-silicide so that the remaining high concentration n-type first polysilicon 4 serves as a source and a drain region to have an LDD structure.
또한, (g)와 같이 사진식각 공정에 의해 소오스/드레인 영역을 제외한 부분의 실리사이드(7)와 제1폴리실리콘(4)을 제거하는데 이때 패드(Pad)로 작용할 수 있도록 충분히 디멘션(dimension)을 확보한다.In addition, as shown in (g), the silicide 7 and the first polysilicon 4 in the portion excluding the source / drain regions are removed by a photolithography process. In this case, the dimension is sufficiently dimensioned to act as a pad. Secure.
이어 (h)와 같이 절연층(8)을 증착하고 콘택을 형성하여 메탈(9)을 증착한다.Next, as shown in (h), the insulating layer 8 is deposited and a contact is formed to deposit the metal 9.
이상과 같은 공정으로 제조되는 본 발명에 의하면 기판(1) 표면에 바로 실리사이드(7)가 형성되지 않고 제1폴리실리콘(4) 위에 실리사이드(7)가 형성되어 기판 (1)의 손상을 방지할 수 있음은 물론 디램급 소자의 메모리 셀에서 형성하기 어려운 LDD구조를 이룰 수 있으며, 자기정합의 이득을 증가시킬 수 있는 유익한 특징이 있는 것이다.According to the present invention manufactured by the above process, the silicide 7 is not formed directly on the surface of the substrate 1, but the silicide 7 is formed on the first polysilicon 4 to prevent damage to the substrate 1. Of course, it is possible to form an LDD structure that is difficult to form in a memory cell of a DRAM device, and there is an advantageous feature to increase the gain of self-matching.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015998A KR940006675B1 (en) | 1991-09-13 | 1991-09-13 | Manufacturing method of mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015998A KR940006675B1 (en) | 1991-09-13 | 1991-09-13 | Manufacturing method of mosfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930006961A KR930006961A (en) | 1993-04-22 |
| KR940006675B1 true KR940006675B1 (en) | 1994-07-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910015998A KR940006675B1 (en) | 1991-09-13 | 1991-09-13 | Manufacturing method of mosfet |
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|---|---|
| KR (1) | KR940006675B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030010371A (en) * | 2001-07-26 | 2003-02-05 | 변재홍 | Exhaust smoke purification Device of Internal Combustion Engine |
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1991
- 1991-09-13 KR KR1019910015998A patent/KR940006675B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR930006961A (en) | 1993-04-22 |
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