KR940006081B1 - Semiconductor memory device controllable current spending - Google Patents

Abstract

The device consists of a decoder which decodes given incoming addresses, a driver which puts a output signal from the decoder into an input node, and amplifies that signal to drive memory cell, a wordline driver which is inserted between a driver and a decoder and consists of discharge elements to discharge a voltage applied to the input nodes of the driver when the memory cell is unselected, and a capacitor which is inserted between the input nodes of the driver and a ground to restrain the voltage going up when the memory cell is unselected.

Description

Semiconductor memory device with suppressed malfunction and standby current consumption

1 is an embodiment of a word line driver circuit according to the prior art.

2 is a voltage waveform diagram of FIG.

3 is another embodiment of a word line driver circuit according to the prior art.

4 is a voltage waveform diagram of FIG.

5 is a word line driver circuit diagram according to the present invention.

6 is a voltage waveform diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to circuits for driving memory cells.

As the semiconductor memory device is highly integrated, the failure rate of the memory chips is increased. Therefore, in the current bandome memory device, it is necessary to mount a redundant memory chip to replace the defective memory chip with the bad memory chip. The operation of replacing the defective memory 쎌 with the redundant memory 이라 is called a repair operation, and in order to perform the repair operation, a decoder circuit for decoding a predetermined address is required. Thus, the decoder circuit drives a predetermined selected memory chip, which is divided into a normal decoder circuit for driving a memory chip in a normal memory array and a redundant decoder circuit for driving a memory chip in a redundant memory array. . A predetermined fuse is inserted between the normal or redundancy decoder circuit and the memory chip, and a predetermined memory chip is selected or deselected depending on the cutting of the fuse. In the following description, for convenience of description, the decoder circuit, the fuse, and the like provided to select a word line of the memory V from a predetermined address are collectively referred to as a word line driving circuit.

In this regard, the word line driving circuit shown in the related art is shown in FIG. The voltage waveform diagram of FIG. 1 is shown in FIG. The configuration of FIG. 1 is a partial circuit diagram of the static RAM, in which the components of the decoder circuit are well known in the art and are not related to the gist of the invention. The conventional word line driver circuit 50 includes a decoder circuit 10 for inputting and decoding a predetermined address, a fuse f1 connected to an output terminal of the decoder circuit 10, and A resistor terminal 20 inserted between the fuse f1 and the memory V30 to amplify the output of the decoder circuit 10 and a resistor connected to n1 which is an input node of the driver stage 20. And (R).

The operating characteristics of the first FIG. Circuit will be described with reference to FIG. After a predetermined address is input and decoded, it is connected to the word line 31 to select a predetermined memory 30 30 according to the address. At this time, when there is no defect in the memory V30 (that is, when it is not defective), the fuse f1 is not cut. However, when the memory V30 turns out to be defective, the fuse f1 is cut (by laser projection or the like). Then, the n1 node connected to the resistance element R becomes the ground voltage Vss level, and thus, the n3 node also becomes the ground voltage Vss level, so that the word line 31 is always in a disabled state. Then, the decoded signal is not transmitted to the n1 node by the fuse f1, which is cut when such a defect is selected in the operation of the chip, and the selected address is a redundancy decoder (not shown). After decoding, the redundant word line (not shown) signal is enabled and replaced with a redundant memory 쎌 (not shown). In the circuit configuration that generates the defective normal word line 31 signal, the n1 node is connected to the resistance element R when the fuse f1 is cut. As a load resistance material of the memory V30, it is generally composed of a high resistance of 10 ⁹ -10 ¹² kV units. The n1 node connected to the resistance element R is connected to the gate terminal of the T1 transistor in the driver terminal 20, wherein a parasitic capacitance is formed between the gate terminal and the power supply voltage Vcc terminal. exist.

Therefore, when the power supply voltage Vcc is powered up and applied to the chip for the first time, the n1 node is caused by the capacitance between the gate and Vcc of the T1 transistor with the increase of the power supply voltage Vcc as shown in the waveform diagram of FIG. Coupling results in an increase in voltage. The voltage charged instantaneously to the n1 node is discharged by the resistance element R, which is usually up to several tens ms to several ms. Therefore, since the voltage level is determined by the voltage of the n1 node, the n2 node cannot be charged to a "high" level capable of driving the T4 transistor. Thus, during the period in which the n1 node is discharged to the ground voltage (Vss) level after the first power-up to the chip (that is, within the t1 section of FIG. 2), the test of the chip is started and the If the memory chip 30 is selected, since the normal word line 31 is in a "high" state during this period, a bad chip is selected and the chip malfunctions. At this time, the n1 node is at an indeterminate voltage level, not at the "high" level or the "low" level, so that a DC current is generated through the channels of the T1 and T2 transistors, so that the standby time during the test of the chip within the t1 period is achieved. This causes current failures such as stand-by leakage current or excess current.

Another word line driving circuit conventionally proposed in FIG. 3 is shown in FIG. 3 to compensate for the above-described problem of the FIG. 1 circuit. The circuit of FIG. 3 replaces the high resistance element R of the circuit of FIG. 1 with the transistor Tn which is always " turned on ". Other components are the same as those of FIG. The voltage waveform diagram of FIG. 3 is shown in FIG. 4 and the operating characteristics of FIG. 3 will be described with reference to FIG. The circuit of FIG. 3 has an NMOS transistor Tn connected to a gate to a power supply voltage so that the discharge time is fast, so that, for example, the potential of the n4 node when a predetermined memory pin is found to be bad and disabled. Is discharged through the enMOS transistor Tn (as shown in FIG. 4 above) in a short time. In this case, the NMOS transistor Tn makes the channel size small in order to reduce the current value consumed through the channel while the word line 31 is selected and enabled “high”. However, this does not fundamentally solve the problem that occurred in the same circuit as the first degree.

That is, the fuse f2 connected to the word line 31 is de-selected when the memory V30 of the chip including the FIG. 3 circuit is found to be defective. It is cut to deselect the word line 31. However, at this time, when the chip is powered up, the n4 node, which is an input node of the T5 transistor, has a voltage increased due to the capacitance between the gate and Vcc of the T5 transistor. This elevated voltage is discharged through the channel of the Tn transistor. However, at this time, as shown in FIG. 4, the time for which the elevated voltage of the n4 node (small in size) is discharged through the channel of the Tn transistor becomes inversely proportional to the size of the Tn transistor, which is The malfunction of the chip due to the delay of the rising time and the discharge time due to the Vcc coupling voltage of the FIG. 1 circuit is not completely solved. However, since the resistance value of Tn in FIG. 3 is smaller than the resistance R value in FIG. 1, the discharge time of the elevated voltage is relatively short (t1 > t2), and the enable state of the WL 31 is shown in FIG. It is shorter than the WL enable period. In addition, the elevated n4 node voltage generates a direct current through the channels of the T5 and T6 transistors, resulting in a standby current failure during the test of the chip.

Accordingly, an object of the present invention is to provide a word line driving circuit which prevents chip malfunction and standby current failure during test of the chip.

In order to achieve the object of the present invention, the present invention provides a decoder circuit for inputting and decoding a predetermined address and an output signal of the decoder circuit to a predetermined node and amplifying the signal to obtain a predetermined memory chip. A word line driver circuit having a driver circuit for outputting as a driving signal and a discharge element for discharging a voltage of an input node of the driver circuit inserted between the decoder circuit and the driver circuit, comprising: an input node of the driver circuit; It is characterized by comprising a suppression element connected to a predetermined ground voltage terminal for suppressing the voltage rise of the input node. In the above, the suppression element is provided in a normal memory array.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 shows a word line driving circuit of a semiconductor memory device including the suppressing element according to the present invention. 6 shows a voltage waveform diagram when the circuit of FIG. 5 is powered up.

In FIG. 5 according to the present invention, the decoder circuits 60 and 60 ', the driver circuits 70 and 70', and the memory chips 80 and 80 'are well known and thus will not be described. A configuration feature according to the present invention is provided with a capacitor CN which is a voltage increase suppressing element between an input node N10 of the driver circuit 70 and a predetermined ground voltage terminal Vss.

Operation characteristics based on the configuration of FIG. 5 described above will be described in detail with reference to FIG. When the chip including the word line driver circuit 100 according to the present invention is tested and the memory 쎌 80 is found to be defective 퓨, fuse F1 is cut to disable the normal word line 81. Therefore, when the address for selecting the memory chip 80 is applied, the redundant memory chip 80 'is selected. The power supply of the driver circuit 70 when the chip for which the repair operation is completed is tested again or when the address for selecting the memory chip 80 is applied while powering up the chip in other cases. As the voltage increases to the voltage Vcc terminal, the N10 node, which is an input node of the T10 transistor, is increased by a parasitic capacitance between the gate and Vcc of the T10 transistor. However, the rising voltage at this time is extremely weak, which is achieved by the capacitor CN.

That is, even if the voltage of the N10 node rises due to the parasitic capacitance between the gate and Vcc of the T10 transistor, it is accumulated in the capacitor CN (that is, the N10 node side terminal), and the accumulated voltage is stored in the capacitor ( It is discharged immediately by the coupling effect of CN). (In other words, since the capacitor CN is connected to the ground voltage Vss terminal, the voltage accumulated in the capacitor CN is directly discharged due to the coupling effect of the capacitor CN.) Thus, the N10 node. The chip is powered up to increase the voltage at the power supply voltage Vcc terminal of the driver 80 circuit, thereby suppressing the voltage increase due to parasitic capacitance between the gate and Vcc of the T10 transistor. Therefore, the word line 81 selecting the memory 80 80 remains disabled so that no chip malfunction occurs. In addition, since the voltage of the N10 node does not become a voltage that simultaneously "turns on" the T10 and T20 transistors due to the suppression effect of the capacitor CN, the DC current does not occur in the driver circuit 70. This prevents standby current failure during the test.

On the other hand, in FIG. 5, when the memory chip 80 is normal, the driver circuit 70 operates like a normal driver circuit. In other words, the fuse F1 remains connected so that the output of the normal decoder 60 performs a normal decoding operation of selecting the memory 쎌 80. At this time, the output of the redundancy decoder 60 'is grounded, and the word line 81' of the redundancy memory V 80 'is grounded, and the selection operation of V is not performed. It should be noted that the capacitor CN does not affect the discharge of the voltage applied to the N10 node when the normal word line 81 is selected. This is because the voltage and the time applied to the N10 node when the word line is selected and the rise and sustain time of the voltage due to the parasitic capacitance between the gate and Vcc of the T10 transistor when the power-up of the power supply after the Fuse F10 is cut. Because there is a big difference. As is well known in the art, the normal decoder 60 is responsible for supplying and discharging the voltage across word line 81. Therefore, when the voltage is applied to the N10 node, discharge through the NMOS transistor (TN) and the capacitor (CN) as a resistor becomes somewhat, but this is not an amount that makes it difficult to select word line 81, and at the same time, This is because the voltage is much higher than the voltage raised by the parasitic capacitance between the gate and Vcc of the T10 transistor at power-up after the Fuse F10 is cut, which is easily understood by those skilled in the art. There will be.

As shown in FIG. 6, the voltage of the word line 81 that selects the memory chip 80 is increased by the capacitor CN even when the chip is powered up. Lower, thereby making the operation of the chip stable. In detail, the chip is powered up in FIG. 6 so that the power supply voltage rises from 0V to the Vcc level (which is a normal normal power supply voltage level) so that the voltage is applied to the power supply voltage Vcc terminal of the driver circuit 70. As the voltage rises, the N10 node, which is an input node of the T10 transistor, temporarily increases due to parasitic capacitance between the gate and Vcc of the T10 transistor. Here, when the capacitor CN is configured as shown in FIG. 5, the parasitic capacitance between the source terminal of the PMOS transistor T10 and the N10 node and the components of the capacitor CN according to the present invention are connected in series. Becomes Thus, even if the power supply voltage is increased by the relatively large capacitor CN, the voltage applied to the N10 node is accumulated in the capacitor CN (that is, the N10 node side terminal), and the accumulated voltage is stored in the capacitor ( Direct discharge by the coupling effect of CN) causes the level to be extremely weak and does not rise to the level at which T10 or T20 is tripped as shown in FIG.

Meanwhile, it should be noted that the size of the capacitor CN, which is a voltage suppressor according to the present invention, can be adjusted to have an appropriate capacitance value according to the operating speed of the chip and the size of the driver circuit 70.

As described above, the word line driving circuit according to the present invention includes a voltage increase suppressing element at an input node of the driver circuit, thereby preventing the generation of direct current, suppressing the consumption of standby current, and preventing chip malfunction. Improve the operating characteristics of the chip.

Claims (2)

A decoder circuit 60 for inputting a predetermined address and decoding the same; and an output signal of the decoder circuit 60 to a predetermined input node N10, amplifying the signal, and amplifying the predetermined signal; Is inserted between the decoder circuit 60 and the driver circuit 70, and outputs the signal as a driving signal 81, when the memory chip 80 is unselected. A semiconductor memory device having a word line driving circuit comprising a discharge element TN for discharging a voltage applied to an input node N10, wherein the word line driving circuit is an input node N10 of the driver circuit 70. And a suppression element connected between a predetermined ground voltage (Vss) terminal and suppressing a voltage rise of the input node N10 when the memory V80 is deselected. Semiconductor memory device . The semiconductor device according to claim 1, wherein the suppressing element is formed of a capacitor (CN) by connecting both ends of an electrode between an input node (N10) and a ground voltage (Vss) terminal of the driver circuit (70). Memory device.