KR940004996Y1 - High-speed processing system for plc sequence instructions - Google Patents

Abstract

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Description

PL's sequence instruction high-speed processing system

1 is a block diagram of a PLC command process according to the prior art.

2 is a block diagram of a high-speed sequence instruction processing system of the present invention PL.

3 is a processing table of the subject innovation register.

* Explanation of symbols for main parts of the drawings

11: pulse generator 12: program counter

13: Program memory 14,15: Upper latch part

16: lower latch portion 17: shift register portion

18: Operation logic part 19: Code reading and signal generation part

20: address generator 21: data memory

OR: Oagate

The present invention relates to a high speed processing of a sequence command of a programmable logic controller (PLC), and more particularly to a high speed processing system of a sequence command of a PLC that is suitable for high speed PLC, confidentiality, and miniaturization of a PLC.

FIG. 1 is a block diagram of a conventional PLC instruction processing by this PROM, and as shown therein, the output side of the pulse generator 1 is connected to the input side of the program memory 3 via the program counter 2, and the program of FIG. The output side of the memory 3 is connected to the input side of the data memory 7 via the pyrom 4, the latch portion 5, and the latch portion 6, respectively. It was configured to be connected to the control signal generator 10 through.

The processing operation of the conventional PLC instruction configured as described above is as follows. By the command of the central processing unit (not shown in the drawing), the pulse generator 1 operates, and the upper code data of the program memory 3 is output by supplying the address of the program counter 2 so that the pyramid 4 ( As it is supplied to the address of 8), the data already stored in the pyrom 4 and 8 are output. That is, one of four states to process the instruction data (S _1, S _2, S _3, S ₄₎ of the first state is an upper address is output from two feet ROM 4 in the (S ₁₎ via a latch unit (5) The control signal stored in the memory 7 and output from the pyramid 8 is applied to the control signal generation unit 10 through the latch unit 9, and as the counter of the program counter unit 2 increases by one. The lower address of the pyramid 4 is output and applied to the data memory 7 and the contents of the data memory 7 and the control signal processing unit ₃ in the third state S ₃ and the fourth state S ₄ . One instruction is processed as a result of the calculation with the shift register (not shown) connected to the output side of 10).

However, such a conventional sequence instruction processing method has a problem that the processing speed is slow due to the time consumed in the access time of the pyrom.

In order to solve such a conventional problem, the present invention speeds up the processing speed by processing a sequence command of a PLC with a TI gate, and manufactures a circuit of all blocks into a single gate array to reduce the device size and circuit pattern. A circuit capable of eliminating interference caused by the present invention is described in detail with reference to the accompanying drawings. 2 is a block diagram of a sequence instruction high-speed processing system of the present invention PLC, as shown therein, by inputting the basic clock from the basic clock input terminal (C ₁ ) by the start command of the central processing unit (not shown) A pulse generator 11 for generating four pulse states S ₁ , S ₂ , S ₃ , and S ₄ , and a program counter for inputting an output signal of the pulse generator 11 to counter a predetermined pulse. (12), a program memory 13 for outputting predetermined data designated according to the input signal of the program counter unit 12, and output data of the program memory 13 in the states S ₁ and S ₂ . The address generator 20 for inputting the latching upper and lower latch parts 14 and 15 and 16 and the output data of the upper and lower latch parts 15 and 16 to output addressing data. And inputting the output data of the address generator 20 And a data memory (21) for outputting itaconic, state (S ₁₎ the upper 8 bits determine the hardware processing is enabled and generates the code reading and signals for controlling read / write of Sykes data memory 21, unit 19 is read in And a shift register unit 17 for performing a shift process and an arithmetic logic unit 18 for performing arithmetic processing when the code reading and signal generation unit 19 determines that hardware processing is possible. Referring to Figure 3 attached to the action and effect will be described briefly as follows.

By the start command of the central processing unit a pulse generating unit 11 is to input the base clock four states to process one of the commands in _{(S 1, S 2, S} 3, S 4) first, in a state (S ₁₎ The upper code of the instruction output from the program memory 13 is latched through the upper latch unit 14 so that the upper 8 bits of data are inputted into the code reading and signal generating unit 19 and the upper latch unit 15 The upper nibble of the data is outputted by being the upper nibble address of the memory 21, and the lower code of the instruction output from the program memory 13 in the state S ₁ is provided through the lower latch unit 16. Is applied to the address generator 20, and the output signal of the address generator 20 is applied to the input side of the data memory 21 by the enable signal of the OR gate OR ₁₁ in the states S ₃ and S ₄ . do. In addition, the control signal is configured so that the read / write operation of the data memory 21 is performed, and the shift register unit 17 is processed as shown in FIG. 3 so that the shift register unit 17 is processed according to the output data of the upper latch unit 14. ) state (L _0, to construct an L ₁₎ for example, input command (operation data of the state (S ₃₎ computation jojikbu 18 after the shift process in the case of LoAD, aND, OR) processing, and is the The result is reloaded in the state S ₄ to complete one cycle, and in the case of the output instruction OUT, SET, or RST, the state S ₄ is shifted in the state S ₄ without processing of the shift register 17 in the state S ₄ . One cycle is completed after writing the output data of the register section 17 and the calculation organization section 18 to the data memory 21.

However, the load instruction AND / OR latches and right shifts the output data of the calculation organization unit 18 in the state S ₃ , and then AND / ores the data of the new calculation organization unit 18 to result in the state S. Reload in ₄ ) to complete one cycle.

As described in detail above, the PLC command is processed by the TI gate to enable high-speed processing, and all blocks are manufactured in one gate array to prevent interference by a circuit pattern.

Claims (1)

Output data of the pulse generator 11 for generating four pulse states S ₁ , S ₂ , S ₃ , and S ₄ outputs predetermined data stored in the program memory 13 through the program counter 12. In the sequence instruction processing circuit of a PLC which performs arithmetic processing, in the state S ₁ , the upper 8 bits of data of the program memory 13 are shifted to the shift register unit 17, the arithmetic organization unit 18, the code reading and signal generating unit ( 19), respectively, to be applied to the data memory 21, and to allow the lower 8 bits to be applied to the data memory in the state (S ₂ ), and in the states (S ₃ , S ₄ ) And a sequence command high speed processing system of a PLC, characterized in that the data applied to the computing organization unit 18, the code reading unit and the signal generating unit 19 are respectively processed.