KR940002657Y1 - Capacity enlarging circuit for hard disk driver - Google Patents

Abstract

No content.

Description

Capacity increase circuit of hard disk driver

1 is a capacity increase circuit diagram of the present invention.

Fig. 2a-g or Fig. 1 is a waveform diagram of each part.

* Explanation of symbols for main parts of the drawings

1: Delay unit OP1: Operational Amplifier

Q1-Q3: Transistor C1-C5: Capacitor

The present invention relates to an increase in capacity of a hard disk driver, and in particular, a capacity increase circuit of a hard disk driver that increases capacity and reliability of a system by reducing a pulse width of a signal output from a head to improve phase gain. It is about.

In general, in order to increase the capacity of a hard disk drive, the recording density must be increased. Therefore, when the recording frequency is increased, the number of bits per unit length increases, thereby increasing the capacity. However, increasing the capacitance in this way increases the phase shifting, resulting in a defect in the error rate (Error Rate) characteristics.

Therefore, the present invention was devised to eliminate the above defects, and is to improve the phase gain by reducing the pulse width of the signal output from the head, which will be described in detail with reference to the accompanying drawings.

1 is a capacitance-increasing circuit diagram of the present invention, in which the head output signal, which is an early signal, and this signal are delayed by the delay unit 1 for a predetermined time T, and then again for a predetermined time T. Low-pass emitters of transistors Q1, Q2, and Q3 that shape the waveforms of the normal and rate signals respectively output from the output terminals NP and LP, respectively, After the filter capacitors C1, C2, and C3, the emitter of the transistor Q1 is connected to the narrow-band filter resistor R12 and the capacitor C5, and the differential amplifier associative amplifier OP1 is connected. And the emitters of the transistors Q1, Q2, and Q3 through the non-inverting input terminals of the transistors R6, R7, R8, and R9, respectively. The inverting input terminal of the amplifying associative amplifier OP1 is configured to be connected in common, and its operation and effect will be described with reference to FIG.

The head output signal, which is the early signal shown in FIG. 2A, is delayed by the delay unit 1 for a predetermined time T, and is output from the output terminal NP as the normal signal shown in FIG. 2B, and again delayed by the predetermined time T. Is output from the output terminal LP as the rate signal shown in FIG.

The delay time T is determined according to the characteristics of the system.

The normal signal is shaped by the transistor Q1 and applied to the non-inverting input terminal of the operational amplifier OP1 for differential amplification through the low pass filter capacitor C1, and through the resistors R6 and R7. Q2) and Q3 respectively shape the waveform, and the second signal at a constant ratio (K) by the rate signal and the early signal and the resistor (R7-R9) through the low-pass filter capacitors (C2) and (C3). They are synthesized together and applied to the inverting input terminal of the operational amplifier OP1 for differential amplification.

The K value at this time is determined by the resistance (R7-R9), which is also determined according to the characteristics of the system.

to be.

In this way, the composite signal of the early and rest signals applied to the inverting and non-inverting input terminals of the operational amplifier OP1 for differential amplification and the normal signal are subtracted as shown in FIG. After filtering by the narrow-band filter, a signal having a reduced pulse width as shown in FIG.

In the above-described pulse detection unit, the effect of noise is eliminated by using a circuit unit for detecting a predetermined voltage or a maximum voltage.

As described above, the hard disk driver increases the capacity by reducing the pulse width of the head output signal when the recording density is increased for increasing the capacity, thereby improving the characteristics of the phase gain and error rate, thereby improving the reliability of the device. There is.

In addition, the present invention can be applied to a floppy disk driver having a similar read / write channel.

Claims (1)

A head output signal which is an early signal and a normal signal which is delayed by the delay unit 1 for a predetermined time T, again a predetermined time T, and output from the output terminals NP and LP, After the emitters of transistors Q1, Q2, and Q3 that shape the waveform of the rate signal through capacitors C1, C2, and C3, respectively, resistors R6, R7, R8, Through R9, the narrowband filter of the resistor R12 capacitor C5 is commonly connected to the inverting input terminal of the operational amplifier OP1 connected thereto, and is commonly connected to the inverting input terminal of the transistor Q1. And the emitter of (Q1) connected to the non-inverting input terminal of the operational amplifier (OP1) through the capacitor (C1).